PCI-Sig Releases 256GBps PCIe 6.0 X16 Spec
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I'm sure on the plus side there will be a huge resale market for "combination computer and room heater" :-)
In fact, on the surface, I would think that "traditional" databases (i.e., those residing on actual storage devices) would be more likely to benefit enormously as a result of this "upgrade" -- because of the massive increase in available bandwidth for storage and networking, of course.
--
(I'll certainly admit thatI don't follow or keep up with developments in new generations / iterations of Intel processors / hardware architectures, but I'm assuming that Intel's Xeon CPUs still access RAM via their own memory controller. Intel has definitely done (more than) their fair share of stupid shit over the years but I'm guessing they haven't recently decided that, now, the proper place for system memory is on the PCI-e bus!)
Vendors are moving towards bringing the main ram closer, to increase bandwidth, reduce power and reduce latency. However, this will necessarily mean that the amount of ram a CPU has will be fixed -- there will be no more dimm slots.
So what if you need more ram than the market provides on the top-end cpu? Samsung has your back, with CXL.memory. [0]
[0] https://www.anandtech.com/show/16670/using-a-pcie-slot-to-in...
High End Accelerators: HBM
Consumer: maybe on-package DDR like M1
Everywhere: more cache
https://www.anandtech.com/show/17067/intel-sapphire-rapids-w...
So -- how do you prove that your infrastructure can blow the socks off everything without building two of them and testing?
So a lot of the reason for using some of these high end scopes/analyzers is bypassed by the testing/diagnostics functions on the serdes itself. And then of course there are a ton of signal tuning parameters which get programmed during link training.
Even modern analyzers have problems with this, and I've seen vendors that instead of even trying to reconstruct the signal at the endpoint use virtual transmission models and require one to probe at the source.
This is one of those areas that I bump into every couple years, and its frequently quite educational.
A BNC-to-PCIe-lane board with some signal conditioning would make for a hilarious oscilloscope.
This makes me smile. When I left PHY testing a few years ago SMA was no longer keeping up with the > 25 GBaud PAM4 standards coming out.
BNC was useful for PHY development in the 90s.
If nothing else it would make hardcore overclockers step up their game and start talking more about signal integrity. :)
Each PCIe lane is an independent SERDES. Its not like a parallel memory controller where they share a clock, when you have x16 lanes, you have 16x independent streams you're shoving to the device downstream.
Any communication protocol has functional layers to them, and at the very bottom is what's called the Phy layer (or physical layer.) While pretty much every layer can be implemented in digital logic, the physical layer has a lot of analog circuitry. (It's programmable analog circuitry, so it's technically mixed signal.) Most wired communication protocols that you are familiar with (including SAS/SATA, USB, HDMI/DP, PCIe/NVMe, and Ethernet) all use what's known as a "SerDes Phy" which is short for Serializer Deserializer. It takes parallel data in, and serializes it to transmit data, and does the reverse when receiving data. In the example of PCIe Gen 4, it takes 32 bits of data in at 500 Mb/s (per bit) and serializes it to 16 Gb/s.
Because the SerDes Phy is such a common part of all communication protocols, it's often reused in other designs. For example - a GPU may use the same SerDes Phy design for its PCIe lanes as it does for its HDMI ports (at least on the transmit side.) They are however programmed differently.
Because these designs see so much reuse in so many different chips, there are companies that specialize in designing SerDes Phys, and their development is usually ahead of protocol development. Though in today's day and age, it's super complicated, and consists of way more than shift registers and a PLL. But there are SerDes designs that exist in products that are capable of 112Gb/s (not sure if 224Gb/s exists outside of test chips yet.)
You can buy modern FPGAs that have PCIe Gen 5, but with a SerDes Phy capable of going way faster. And if you want, you could bypass that hard block and talk straight to the SerDes, and program your own PCIe 6.0 controller.
But to answer your question on how they prototype it and test it, they run computer simulations that are exceedingly complicated and slow, and once a test chip comes back from the fab, eye diagrams are usually collected using what's known as a repeating signal scope. Since it's insanely difficult to sample a 112Gb/s signal at any reasonable resolution, it's sampled statistically (in time) over billions of samples, and plotted by knowing the frequency of the target signal. An eye diagram is what comes out of a traditional NRZ (non return to zero) where each cycle represents either a 1 or a 0. In an eye diagram, you see all permutations of bit transitions overlayed on each other, since you're sampling billions of cycles statistically. This is important because you can see other anomalies of your signal like jitter and rise/fall times.
There's a lot more to it, and this comment is already getting to be a wall of text but definitely feel free to ask more questions!
Could switching to PCIe instead of Ethernet for the digital signaling have better performance? I don’t know but I doubt it. Ethernet is hitting 100gbps and higher and I suspect the challenge is designing cabling that can hit just as much as the analog design piece. Not to mention that USB3.2 and Ethernet have very similar speeds, just Ethernet can manage it over much longer distances at significantly lower cost. I’m skeptical PCIe has some kind of magic bullet here. These protocols are optimized for totally different use cases.
I think the reason why it costs a lot is that packets are still tiny, and ports are many. A quality 16 port, 10 Gb switch is expected to have no internal bottleneck, able to handle every port being used to full capacity at once. And that works out to 320 Gbps bandwidth in the whole switch.
Then there's that thanks to the Internet, we're still stuck with 1500 byte packets, which means best case we're dealing with 812,744 pps, and worst case, we're dealing with 14,880,952 pps. And that's on one port.
With the later number, your time budget per packet is 67ns. And if you start looking, context switches, cache misses, locks, etc all have times also measured in nanoseconds.
It's getting very, very tight and requires extremely careful programming to actually make this work. And of course in modern times, we have firewalls, NAT, statistics, routing, etc all of which cost precious time out of this budget, and which are all user-configurable, so it's something that's difficult to just shove into a purpose-built chip to take that load off the CPU.
PCIe has the advantage of that it doesn't have to deal with half the crazy stuff networking involves.
> 16 port, 10 Gb ... 320 Gbps bandwidth in the whole switch
That's a nice switch. Expensive, but nice. Let's do the math on a modern low-end consumer CPU:
PCIe: 20x 32Gb/s x2 = 1280Gbps
Chipset: 8x 16Gb/s x2 = 256Gbps
Display: 4x 4x 12Gb/s = 192Gbps
...and if we compared the switch to a CPU in its own price bracket, this would go from silly to ludicrous.
Look, I'm not asking for a battery of 400GbE ports on every laptop, but USB can deliver 10Gb/s across a few meters for a few dollars while Ethernet wants a few hundred dollars to ship the same bits over the same distance, and that's unfortunate.
People keep trying to make excuses for Ethernet, but I don't think it deserves their efforts. I think something's broken in the consumer networking industry -- it feels like they gave up on consumers entirely after 1GbE, and I think we could all benefit if someone breathed some life back into that corner of the market.
How is it even possible to have correctly functioning circuits at such high speeds? I'm guessing at the very bottom of the Phy layer there several transistors switching at incredibly fast speeds. I understand that these transistors have several parameters such as their delay, rise, and fall time. Things most certainly don't happen instantaneously, a few logic ICs I played with also have a propagation delay time specified in their data sheets lasting a few nanoseconds.
Take the deserializer for an example, happening at 16Gb/s, which if I understand correctly equates to 1 bit every 62.5ps (0.0625ns). How does any circuit affected by the parameters I just talked about handle signals at such high speeds?
(Please go easy on me, I know some of my assumptions are probably wrong or oversimplified but I would love to learn more)
One more thing: CMOS historically wasn't the fastest logic family. Bipolar ECL was faster, but it burned a ton of idle current, so it ran into power limitation long before CMOS.
In either case, thermal limits prevent you from using these speeds across the whole chip, but just because your thermal budget can't afford 10,000,000,000 speed demons doesn't mean it can't afford 1000 of them in a few SerDes :)
But yeah, decades of Moore's law have not gone to waste, and those discrete logic chips are frozen in time. It's a neat reminder of how far we have come!
I work on the Hardware/Software interface quite a bit (more in the past than now) and this is always fascinating, I'm on the Software side, thanks for the details!
The encoding takes 8 bits and turns them into 10 for DC balance and to help the clock recovery system. You are basically losing 20% of your bandwidth to encoding overhead.
PCIE Gen 3 and above have switched to 64b/66b encoding for less overhead.
Generally, if you are wondering what PCIe does, the answer is usually "they do the hardest, fastest, highest-performance thing and they do it so well that nobody notices."
Not even close, and there are 5 paragraphs. Also, really well written.
PCI SIG has regular validation events and beyond that the lab where I cut my teeth is well renowned for hosting plugfests for cutting edge technologies.
Also, I remember playing around with PCI implementation on FPGAs over a decade ago and timing was already not easy. What goes into creating a PCIe Gen4/5 device these days? How can you actually achieve that when you're designing it? Are people just buying the chipsets from a handful of producers because it's unachievable for normal humans?
EDIT: What's inside the spec differences between say gen 3 and 6 that allows for so many more lanes to be available?
Like 2 years.
When PCIe 3.0 was getting popular, 4.0 was finalized. When 4.0 was getting popular, 5.0 was finalized. Now that PCIe 5.0 is coming out (2022, this year), PCIe 6.0 is finalized.
We seem to be back to a faster cadence now however.
PCIe standards are including more and more coherent-memory options. It seems like PCIe is trying to become more like Infinity Fabric (AMD) / UltraPath Interconnect (Intel).
If anything, the higher-bandwidths of future PCIe-specs would allow the CPU to access the dedicated GPU VRAM at its full speed, rather than PCIe-limited speeds.
So far CXL is pretty strictly a leader/follower type approach, not really suitable for a more symmetric relationship like you have in a multi-socket system. But maybe one day..
Just a few years ago I was trying to explain to an IT manager that 200 IOPS just doesn’t cut it for their biggest, most important OLAP database.
He asked me what would be a more realistic number.
“20,000 IOPS is a good start”
“You can’t be serious!”
“My laptop can do 200,000.”
> “My laptop can do 200,000.”
Only now (PCIe 4 and very recent controllers etc) are the very latest top-end NVME drives hitting around 150k IOPS (which isn't stopping manufacturers from claiming ten times that; WD's NVME drive tests at around 150-200k IOPS and yet they claim 1M) and only in ideal circumstances...reads and writes coming out of the SLC cache, which typically under 30GB, often a lot smaller except in the highest-end drives.
Many drives that claim to reach that sort of performance are actually using Host Backed Cache, ie stealing RAM.
IOPS on SSDs drops precipitously once you exhaust any HBC, controller ram, SLC cache, mid-level MLC cache...and start having to hit the actual QLC/TLC. In the case of a very large database, a lot of IO would be outside cache (though certainly any index, transaction, logging, etc IO would likely be in cache.)
If you meant IOPS with a queue depth of one, or sustained write IOPS, then you need to specify those extra conditions before calling vendors liars.
No high-end drives implement the NVMe Host Memory Buffer feature, let alone rely on it for maximum performance.
You can buy an Enterprise QLC drive that is fully capable of 800k IOPS for reads. TLC drives that can do twice that are available. Those drives don't have SLC caching.
[1] https://ark.intel.com/content/www/us/en/ark/products/series/...
[2] https://ark.intel.com/content/www/us/en/ark/products/134598/...
[3] https://ark.intel.com/content/www/us/en/ark/products/132214/...
It is not just about getting a product out ( i.e PCI-E 6.0 SSD ), but also the platform support. ( i.e Intel / AMD Motherboard support for PCI-e 6.0 )
Product Launch are highly dependent on Platform support. So far Intel and AMD dont have any concrete plan on PCI-E 6.0, but I believe Amazon could be ahead of the pack with their Graviton platform. Although I am eager to see Netflix's Edge Appliance serving up to 800Gbps if not 1.6Tbps per box.
It seems they took the original Zen motherboards with Gen3 and just swapped out the CPU. Only the Zen 3 has a refreshed motherboard. Makes me now check things more carefully to be sure.
We needed that machine yesterday, and it's seen maybe 2 minutes of downtime in the past couple years, so I couldn't send it back. My fault for not specifying I wanted the .v2 of the barebones when ordering it over the phone I guess..
That miracle is somewhat over. They're not going to be able to drive phase noise down below 1 femtosecond, so 6.0 changes tactics. They are now using a fancy encoding on the wire to double the number of bits per symbol. Eventually, it will look more like wifi-over-copper than like PCI. Ethernet faster than 1gbps has the same trend, for whatever it's worth.
A 25 foot cable on monoprice costs $6.49 for cat5e and $7.99 for cat6. It doesn't matter at all.
I could get cat8 for $22.49! Compared to what you're plugging that into for 25/40Gbps that's nothing.
The last batch of cables I bought was 5x 10 foot cat7, for $22 total. (You're not 'supposed' to put normal plugs on cat7 but nobody really cares.)
At the same time, 10 Gbps on fiber is low power and great speed, but the form factor of SFP+ is simply too big for any laptop of 2022. In theory USB-C 3.2 @ 10Gbps to SFP+ fiber adapters are possible, but fiber is not popular outside server rooms, so there is no market for it.
As I said, never. It is not a matter of PCIe speeds, but a technology one: copper is power hungry and requires new cabling, fiber has no cabling.
So, there probably isn't a good reason for not putting it in a laptop. Like wifi, just speed shift it based on load, etc. AKA see 802.3az
So, the old max power draw models from 15 years ago, don't really apply entirely.
How often do you have your laptop plugged into networking but not power? And if that's an important use, I could see manufacturers spicing it up with some power over ethernet to not only fix but reverse the problem.
Though it feels like ethernet ports on laptops are already unsexy at any speed. And you could have the 'balanced' power profile limit the port to 1Gbps on battery.
Mikrotik CRS305 ($150, 4x SFP+) & CRS309 ($250, 8x SFP+) w/ as many S+RJ10s as you want.
Mikrotik quotes 2.7W per transceiver at 10GBASE-T.
https://www.servethehome.com/mikrotik-crs309-1g-8sin-review-...
https://mikrotik.com/product/s_rj10
So yes, it's a bit hot, but definitely something you can get done well under $500 if you want copper.
~$120 per port (assuming 309s, the recommended interleaved spacing, and amortizing the switch cost over # ports) isn't very expensive if (a) you need the capability & (b) already have copper in the walls.
Drywall finishing along will run you that much. :) But yeah, new builds should definitely be fiber.
Wasn't there some network standard that used that trick as well?
Similarly HDR Infiniband also switched to PAM4.
Personally I'm expecting this spec to drive pcie 5.0 adoption into consumer space.
Tbh consumers dont need this througjput. But given that consumer space has remained stuck around 20x lanes off the cpu (plus some for the chipset), the 5.0 and 6.0 specs will be great for those wanting to build systems with more peripherals. A 1x 16GBps link is useful for a lot.
Having that much throughput suggests paging and caching across multiple disks, or using giant models (ml or others) with precomputed lookups in lieu of real-time generation. At any rate, all it takes is a minor inconvenience to overcome and the niche will be exploited to capacity.
Those sound to me like situations where latency will be the bottleneck, even on something like PCIe 3.0 x4.
I can currently only name one consumer use for these super high speed data transfers, and that's loading 3d assets and textures from SSD to GPU in real time based on where you're looking.
For the server market, GPU's and other accelerators, high speed NIC's and SSD's have an unending appetite for bandwidth, so there I expect a lot of interest. But I think we'll see an increasing gap between this and the consumer market, for better or worse.
Nowadays there's all sorts of business cases that require high bandwidth, and the devices to fill them also exist. From NVMe arrays to crazy interconnects to hyper connected machine learning accelerators, PCIe is enabling it all.
PCI-E 6.0 was in research for long because they knew 5.0 would be the end of the way things were working previously.
keywords: PAM4 and 128GBps/per x16 lane(full width, per my understanding, not 256Gbps as title says), which mean it can be used to make a 1Tbps NIC, or any traffic at the scale.
from my reading, we will see pcie6 products mid-2023.
I just spoke to a friend who, as a consultant, was tasked with verifying that a "motherboard" for a projector conformed to the HDMI specs. He'd gotten a bunch of measurements and numbers in a document, and asked if he couldn't get the full spec as it would be easier to understand what to do.
He was told they had the specification but it was at headquarters in Belgium, on a computer that was not connected to the internet. He'd have to fly there, view it on the computer and write off what was needed... which was exactly what someone had done to make the document he'd gotten.
Low volume, expensive products like the one my friend got the job for or consumer products, having to do a recall and board replacement will not be a fun experience for those involved.
[1] https://www.anandtech.com/show/17203/pcie-60-specification-f...
EDIT: Changed PCI to PCIe.
Exactly like PCIe 6.0, but with a slightly simpler negotiation process and none of the fallback modes.
> How much more performant could it be relative to PCIe?
It would have the same performance, but be slightly cheaper to implement.
When two PCIe devices are connected to each other, they don't start in any data transfer mode, they start in a complex autonegotiation mode [0], where they find out the width of the link, the maximum protocol version that each side support, and the maximum speed that the connection between them can support. They were forward-thinking enought to make sure that this process can support pretty much any kind of protocol that does packet switching over LVDS signaling. Since packet switching over LVDS is still the best game in town, they are not overly burdened by backwards compatibility, other than having to also carry all the previous versions with them in the interface controllers. 6.0 changed to a completely different kind of packet system to support FEC, and no-one other than the implementors of the interface controllers have to care.
Because PCIe is so flexible, it won't be unseated until there is some radically new kind of signaling that is better than LVDS on copper, say some kind of optical link. And even then, the successor is almost certain to be a variant of PCIe, just with a new physical layer.
[0]: PCIe LTSSM. I sadly cannot link the spec here because it requires registration but have the diagram someone kindly ripped for SO: https://i.stack.imgur.com/QYyCM.png
For servers it is a different story, but the recent fast move from PCIe ver 3 to ver 5 improved the situation 4x, doubling again is nice, but it does not seem that much of a deal. Maybe moving NICs from the usual 8 lane to a lot less (8 lanes of ver 3 means 2 lanes of ver 5 or a single lane of ver 6) will also make some difference.
EPYC/Threadripper is awesome but also explicitly not the segment being discussed. But since it was mentioned it's 64 PCIe lanes per socket on Intel (up to 8 sockets/512 lanes) instead of 128 lanes for single socket/up to 160 lanes for dual socket on Epyc. Gonna cost you a damn arm and leg and you better know your NUMA though.
In the consumer segment AMD has 16 PCIe lanes for the graphics and up to 4 PCIe lanes for NVMe drives, the chipset link is and additional x4 PCIe instead of a different interconnect. This comes to 20 PCIe lanes for user devices and 4 lanes worth of PCIe bandwidth off the chipset. https://i.imgur.com/8Aug02l.png
Intel offers something similar, 16 PCIe lanes for graphics and 4 PCIe lanes for NVMe. They opt for a proprietary DMI connection to the chipset which is equivalent to 8 lanes of PCIe 3.0 bandwidth or 4 lanes of PCIe 3.0 bandwith. https://i.pcmag.com/imagery/reviews/070BdprI2Ik2Ecd2wzo0Asi-...
Each offers splitting the x16 for the GPU into 2 x8 as well as oversubscribing the downstream PCIe bandwidth from the chipset, devices through the chipset on each obviously hit different latency penalties than CPU direct lanes as well. In the end the offerings are both pretty much identical in the consumer space.
Which lanes are disabled if you use nvme-slot 2. Which slot has which generation etc. A proper nightmare.
And while we are at it, dedicating pci-lanes to nvme-slots must be one of the most boneheaded decisions in modern computers. Just use a pci-card with up to four nvme-slots on it instead.
Based on page 131 of this, it looks like a PCIe lane only uses up six pins.
I'd worry about the die space and the power use but not the pin use.
And that's great since the vast majority don't need that much bandwidth anyway.
Today you typically have a whole slew of devices sharing 4x to the cpu. More bandwidth would open up for more usb and perhaps cheaper onboard 10gig Ethernet etc.
I was hoping AM4 would provide that many lanes on easy to buy motherboards, but it's a meager 28, so not even enough for 2x x16
6.0 transmits 2 bits at a time per lane, 32 billion times a second.
So why are they claiming it's 64 gigatransfers per second? Do I misunderstand the term, or are they trying to pull something cheeky?
https://pcisig.com/blog/pcie%C2%AE-60-specification-released...
> a maximum bidirectional bandwidth of up to 256 GB/s for x16 lanes
But I don't think that's what's happening with the gigatransfers. When they launched 5.0, they were clearly counting one differential pair of pins: "Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration"
But my point is, even though they were already doing that, they were claiming 32GT/s last generation. But it's 64GT/s now. I don't think that's counting more pins, I think they're saying that each transfer is two transfers.
The did pull something cheeky though - the 256 GB/s is for a PCIe x32 connection. It exists in the spec, but I've literally never seen it in the wild.
It's not really that either because PCIe 2.0 was "5GT/s" despite being only 4 gigabits per second.
You could make some kind of argument about pre- and post-encoding bits, but that still falls down in other circumstances. Gigabit ethernet has five voltage levels per lane, 125 milllion times a second. What's its MT/s if the answer isn't 125?
> the 256 GB/s is for a PCIe x32 connection
What makes you say that? The chart says x16.
Sort of, depends on where you're measuring. PCIe 2.0 runs at 5GT/s, which is the speed that the Phy layer runs at, but it uses an 8b/10b encoding, so the Data Link layer sees that 4GB/s. For Gen 3.0 and 4.0 (and I think 5.0) the Phy layer uses a 128b/130b encoding, which has much less overhead. So technically it's about 63Gb/s but we round up. But that's kind of a useless measurement because there's additional overhead from Acks/Nacks on the Data Link Layer and TLP headers on the transaction layer (which depends on the size of your TLPs, and whether or not you're using infinite credits.)
edit: I'm not sure which encoding the Phy layer on PCIe Gen 6.0 uses, since it's PAM4. The (approximately) 63 GB/s on the data link layer assumes 128b/130b encoding
> What makes you say that? The chart says x16.
Maybe that metric includes both directions. Either way, it's misleading, as you only get 128 MB/s (before protocol overhead) on PCIe 6.0 x16. (64Gb * 16 lanes) / 8 bits per byte = 128 MB/s
https://www.intel.com/content/www/us/en/products/docs/progra...
But, I don't think there was room on the pci-e lanes to do something like put a gpu in to use as a DMA buffer to get more ram bandwidth.
I think the next Epyc generation should have PCIe 5 and DDR5, both of which should help.
But, RAM needs at least twice the bandwidth as your network, because you can't have the NIC read from the disk directly, you need to have the disk DMA to ram, and the NIC DMA from ram, and (normal system) ram isn't dual ported, so reads and write contend. If you need to do TLS in software, you touch ram 4 times (disk read, cpu read, cpu write, nic read), so ram bandwidth is an even bigger bottleneck.
From what I recall of the netflix storage node that was linked from HN a few months back, the current generation has 4 x 100 Gb mellanox ethernet ports (CX6, PCIe Gen 4) and somewhere around 20 to 30 PCIe gen 3 NVMe drives.
Assuming they can figure out how to do peer to peer transfers, scaling up by a factor of 4 doesn't seem implausible.
Unless they're really squeezed on power or rack space budget, I would imagine they'd do just fine being a generation back from the bleeding edge.
Also cutting edge is usually very power hungry and power/cooling costs are majority of your expenses at data center scale.
I think this is the case for their open connect appliances (or whatever they call them). They want to try to maximize throughput on a single device so they don't have to colocate so much equipment
PCIe 6.0 1x lane would provide the same bandwidth, meaning you run 1/4th as many wires and still get the same speed.
Alternatively, PCIe 6.0 4x lane will be 4x faster than 4.0, meaning our SSDs can speed up once more.
Today, yes and a few tomorrows as well. But even when a standard is announced as finalized, it can be a long time (Years even) until it makes it's way onto motherboard of the consumer space. By which time, the current goalposts may start looking closer than expected.
I'm just glad they have one number, no endless revisions and renaming of past releases and with that - thank you PCI-Sig.
So, you can just create SSDs that saturate whatever bus you connect them to.
In a sense then, it is the bus specification itself that limits SSD throughput.
The limit then becomes the amount of RAM (or LLC cache if you can keep it there) bandwidth in the machine unless one is doing PCIe PtP. There are plenty of applications where a large part of the work is simply moving data between a storage device and a network card.
But, returning to PtP, PCIe has been used for accelerator fabric for a few years now, so a pile of GPGPU's all talking to each other can also swamp any bandwidth limits put in place between them for certain applications.
Put the three together and you can see what is driving ever higher PCIe bandwidth requirements after PCIe was stuck at 3.0 for ~10 years.
Expect a wave of wacky contenders: SRAM memory banks with ultra low worst-case latency compared to DRAM, low-reliability DRAM (not a good marketing name, I know) where you live with 10 nines of reliability instead of 20 or 30 and in exchange can run it a lot faster or cooler, instant-persistent memory that blurs the line between memory and storage, and so on.
Thank, that it quite an interesting technology I wasn't aware of. Apparently Samsung already made a CXL RAM module for servers in 2021 (1). I wonder how Intel optane would have been if it had used CXL (assuming it didn't).
Side note but AMD devices' (laptops/NUCs) lack of thunderbolt or pcie access is why I'm quite hesitant to buy a portable AMD device which is quite unfortunate. I really hope AMD/their partners can offer a solution soon now that thunderbolt is an open standard.
1. https://hothardware.com/news/samsung-cxl-module-dram-memory-...
Not that I’d be able to use it, but it’s a pity they make the spec available to members only (4000$/year membership) or they sell it at ridiculous prices https://pcisig.com/specifications/order-form
I know that other specifications and even ISO standards are provided for a fee https://www.iso.org/store.html and perhaps something similar should be applied for open source software to avoid similar issues like faker.js and colors.js