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Comment by aappleby | Hacker News Reader

As I understand it asynchronous logic stopped being a common thing decades ago, so those sorts of glitches aren't possible (or less possible?) now. The hard stuff in simulation now is probably handling multiple clock domains.

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Still out there, but only used in special situations. The ARM microcontroller I'm working with has an asynchronous prescaler on the real-time clock crystal input before it gets fed into a second synchronous prescaler which you can then read the output of directly.

This is all about reducing power consumption down in the nA range when the CPU is turned off but the RTC keeps ticking over.

Multiple clock domains definitely tricky though!

As a software-only guy .... multiple clock domains sounds like the same class of problem as multi threaded + parallel programming, right?

Sort of? It's almost more equivalent to networking or distributed processing - circuits in different clock domains can't just send a wire to another domain, they have to go through a synchronizer and do some handshaking and other stuff that's vaguely similar to RPCs. I'm stretching here, it's slightly beyond what I've worked with so far.

Seems like the same as in multithreaded programming, in which you can’t let threads share memory without synchronizing else you get data races and corruption.

it's more like two simple computers talking over serial, and the serial connection bitrate can't be faster than the clock of the slowest of the two computers.

Yep! The microcontroller reference manual is full of warnings to ensure clock rates are compatible by being within a certain range of each other.

Sort of. You have to be careful when signals cross clock domains because they can become asynchronous. So anytime you go from one domain to another, you have to be sure to synchronize the data. This is often accomplished via flip flop.

This is my absolute favorite paper on the topic:

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston...

I’ve only ever seen behavioral solutions for newer systems. At a certain point, logic level designs become unreasonable.

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