TSMC Claims Breakthrough on 1nm Chip Production
techpowerup.com
techpowerup.com
Not only this other source is much more detailed, but it does not contain any word about a "1 nm" TSMC process, which seems to be a pure invention of whoever has written the news at TechPowerup.
The discovery of an appropriate material (bismuth) for electrical contacts to MoS2, which is a semiconductor that can be made in monoatomic layers is indeed extremely newsworthy.
There is no doubt that this discovery might enable much denser semiconductor devices in the future, but nobody could say today which would be the name of the TSMC manufacturing process when they would decide to switch from silicon to molybdenum disulfide and in which year would that happen.
Certainly not in a year or two.
Even a prediction of 5 years would be extremely optimistic for any mainstream components like processors.
MoS2 might become usable earlier for some special devices, but there are a huge number of problems to solve before becoming usable for logic devices, e.g. the development of some logic gates appropriate for this material.
Being able to make CMOS gates does not seem very likely, at least not any time soon.
"Ultralow contact resistance between semimetal and monolayer semiconductors"
First, copper deposition gets more, and more defect prone at small feature size — "bad fill"
Second, even if you get ultra tiny M0, then the contact is rather poor.
At such small dimensions the barrier layer that protects silicon from copper might itself stop behaving like a metal, that's why new interconnects go away from copper for M0 to eliminate the barrier layer.
I wonder, if Bismuth is largely required for large scale production of chips in the future, if it will drive more mining for bismuth, as it typically is a byproduct of other metal extraction, particularly lead. If not, would we then see in an increase in the price of Bismuth? Or is the volume of bismuth required for these chips not enough to drive global price increases?
Enjoy. I have had to link this way too many times while discussing transistor density on this site, apparently it's ingrained that the nanometre figures are mostly bullshit, but not where to actually find a real density figure.
Of particular note is just how far (Density isn't everything but to 1* it'll do) behind Intel 14nm is.
I mean, different parts of the chip have different density, cache, logic, etc. Should it be some specific part or average for the full chip? What if one architecture has massive caches which are denser than logic areas? What about AMD Zen with chips of different nodes? Or should it just be what the manufacturer states as the maximum possible, even if no chip gets close to that stated number, even in dense areas of the chip?
Originally (in true denard scaling land) 2D feature size implied speed and density (which in turn implied power efficiency)... but now that features are distorting into different shapes, those two things are not necessarily directly correlated any more, so perhaps they should be measured separately.
Propagation is the tricky bit because that's where ultimately designs and usable density come into play, but these are only supposed to be rough guides - a few metrics at extremes could be enough, propagation at highest (unrealistic) density, and a density that is possible to continually drive without heat dissipation and power issues.
Though not sure if this would be useful for those who actually work in the industry, maybe we'll just end up with "TSMC 8600" etc there too.
I'm no expert, but that sounds significant.
[0] https://en.wikipedia.org/wiki/Metric_prefix#List_of_SI_prefi...
The (total) qualifier was just because I realize node sizes are measured slightly different depending on the foundry, ie TSMC and Intel mean different things when they say 10nm.
1nm, 500um, 350um, 250um, 180um, 130um, 100um, 90um ...
1nm, 0.7nm, 0.5nm, 0.3nm, 0.2nm, 0.1nm, 0.07nm, 0.05nm ...
1nm, 1/2nm, 1/3nm, 1/5nm, 1/7nm, 1/10nm, 1/14nm ...
1nm, 0nm, -1nm, -3nm, -5nm, -7nm, -10nm, -14nm ...
1nm, 1b nm, 1a nm, 1g nm, 1n nm, 1ac nm, 1ax nm ...
1nm, 360nm, one nm, one x nm, series x nm ...
"TSMC Claims Breakthrough on Cougar Production"
Nah, next odd number smaller than 1nm is simply -1nm lithography.
Or they could go to picometers and femtometers giving another 6 orders of magnitude.
And, of course, 1nm is half of 2nm.
[0] https://spectrum.ieee.org/nanoclast/semiconductors/nanotechn...
Likewise, the materials already in use do decay after a while; I’m not a material scientist, but my friends who are gave me the impression the current flowing though it has a similar effect as does anodising aluminium. This may have been an oversimplification, or not, I wouldn’t know.
Which means... ? Performance degradation? Gates being destroyed long term? Slight decrease at first but then stable performance for years?
I am not the right person to ask what the failure looks like (this may have been an analogy for my benefit rather than how it actually happens), but at some point it fails.
No feature size is really 1nm in any dimension probably not even close.
The definition is more or less arbitrary, TSMC could have released a statement that they made a breakthrough in 1574 Zorks Chip Production and it would be just as true.
The only thing that really matters here are the actual characteristics of the node in terms of power and density both on their own and in comparison to previous TSMC nodes and competing nodes.
It seems that with this specifically the focus was to create as thin layers as possible. Weird shit begins to happen when you have “extreme” geometries or topologies e.g. graphene that has some unique properties when it comes to electrical conductivity due to how electrons move within the lattice.
So it seems that the aim here is to exploit similar effects.
In the beginning, for every doubling of the transistor density, regardless how that was achieved, the marketing size number was divided by about sqrt(2).
More recently the relationship between the density improvement ratio and the marketing size seems to be even less quantitative.
So they might claim that their process is 4 times denser than in the recent IBM announcement or maybe that it is just twice denser, if they have divided 2 nm from IBM by 1.4 and they have rounded to 1 nm.
Similarly, the IBM "2 nm" announcement was probably intended to claim that it is twice denser than the older announcement of the "3 nm" TSMC process.
Also, 0.5 nm for silicon is not the size of an atom, but the length of the edge of a cube with 8 atoms (4 internal atoms, 6x0.5 = 3 atoms on the faces and 8x0.125 = 1 atom in the cube corners).
Nevertheless, there are some very thin layers with a thickness comparable to 1 nm, so corresponding to a small number of atomic layers. Obviously, it is very difficult to grow such thin layers without holes and without variations in thickness.
Moore's law is dead but scaling is not.