IBM achieved 50B transistors in 150mm^2, for a per-transistor area of 3000 nm^2.
TSMC's 5nm process (used by Apple's M1 chip) apparently achieves a transistor area of 5837 nm^2, while Intel's 10nm is lagging at roughly 10000 nm^2.
IBM TSMC Intel Samsung
22nm 16.50
16nm/14nm 28.88 44.67 33.32
10nm 52.51 100.76 51.82
7nm 91.20 237.18* 95.08
5nm 171.30
3nm 292.21*
2nm 333.33
* Estimated Logic Density
Cool. Following along here, I consider that transistors require multiple "features", and these days the more complicated transistor structure has enabled the increase in speed while lowering the power requirements. Power is also now a set of characteristics, the power needed to change transistor state, and the leakage current that remains when the transistor is not switching.
Not just a simple NPN junction FET anymore.
Then I think about those great microchip analyses on Ken Sheriff's blog. How very different transistor layouts show up in circuit designs. I can only imagine that modern high performance SOC design is even more complex.
55 nanometers per transistor sounds like a useful number to me.
Transistor density is weighted number that combines NAND2 transistors/area and scan flip-flops/area.
Tr/mm² = 0.6×(NAND2 Tr/mm²) + 0.4×(scan flip-flop/mm²)
Transistors with 2,3,.. gates are functionally identical to 2,3,.. transistors connected in series, but take chip area that is only a small fraction larger than 1 "normal" transistor. Counting those as either 1, or as multiple (by number of gates) would skew stats in a less-then-useful way.
That is - among other quirks. Ken Shirriff [1] has some excellent articles that touch the topic of what exactly counts as a "transistor".
Properly representing transistor density is a very hard problem, to which many different solutions have been proposed. It's just that the solution typically shows the processes of those who proposed it in the best possible light, so there is no industry consensus.
I could produce a physically smaller transistor, with a smaller gate, source, and drain. However, depending on the limitations of my process changes for scaling I may not actually be able to pack transistors more tightly. Notionally, the smaller transistor could use less energy which improves the chip design, but not be packed more tightly.
There is more than one way to improve a semiconductor at the feature, device, and chip level.
The node naming is a useful convention for the industry because saying something like '10nm' efficiently communicates historical context, likely technological changes, timelines, and other things that have nothing to do with the physical size of the devices on the chips.
It's basically a form of controlled vocabulary.
https://old.reddit.com/r/ECE/comments/jxb806/how_big_are_tra...
https://old.reddit.com/r/askscience/comments/jwgdld/what_is_...
Things like processor caches have similarly low average switching rates, so it doesn't seem out of the realm of possibility to see use of the third dimension for logic.
It's fun to go look back on old CPU coolers. They started around Pentium-era CPUs, then kept getting bigger. Around 100W TDP, they stopped. I think that's the largest practical air-cooled cooler.
Fancier vapor chambers and thicker, higher RPM fans can clear up to thousands in server environments.
To be more specific, one of the things node names have referred to is the M1 (metal 1) half-pitch, or half the center-to-center distance between the metal traces which connect directly (well, almost directly) between transistors. Originally, the closest width you could space those wires was the same as the thinnest width you could make them, since it's basically just a photo negative. If you take the half pitch, that's the width of a wire.
The width of that wire was the thinnest electrode you could make between the n and p regions of silicon, so that was your channel length. Over time we have pushed so that the distance between wires is different from the width of the wires, and the regions of silicon are larger than the distances between them, ect. etc.
So channel length started to shrink much faster than the wires, and in the 2000s it was less than half of the node name and fully a third of the M1 half-pitch. Since then things got even weirder, and "channel length" doesn't correspond to the changes in performance any more.
Since the M1 pitch doesn't track the nodes very well, area density probably won't either. The reason it does so well is probably more to do with the fact that its the other major process goal besides performance- the more transistors you squeeze in, the more chips you get per wafer at a given performance. Foundries ensure the area density keeps increasing as fast as performance, and the difficulty has kept rough pace with performance. It's entirely possible that relative difficulty will change and area density will start to underperform as a metric for performance.
Too many zeroes?