Hacker News Reader

Comment by robocat | Hacker News Reader

Here's the table: "Peak Quoted Transistor Densities (MTr/mm2)"

              IBM    TSMC    Intel   Samsung
  22nm                       16.50  
  16nm/14nm          28.88   44.67   33.32
  10nm               52.51  100.76   51.82
  7nm                91.20  237.18*  95.08
  5nm               171.30    
  3nm               292.21*    
  2nm        333.33

Data from Wikichip, Different Fabs may have different counting methodologies

* Estimated Logic Density

View on HN

I wonder if these logic densities could be converted into units of nanometers. For example 333 MTr/mm2 is 333 Tr/um2. Then there are effectively sqrt(333) transistors on a side of a square micrometer which comes out to about 1/sqrt(333) * 1000 = 55 nanometers per transistor. Way off from the 2 nanometer feature size

> 55 nanometers per transistor. Way off from the 2 nanometer feature size.

Cool. Following along here, I consider that transistors require multiple "features", and these days the more complicated transistor structure has enabled the increase in speed while lowering the power requirements. Power is also now a set of characteristics, the power needed to change transistor state, and the leakage current that remains when the transistor is not switching.

Not just a simple NPN junction FET anymore.

Then I think about those great microchip analyses on Ken Sheriff's blog. How very different transistor layouts show up in circuit designs. I can only imagine that modern high performance SOC design is even more complex.

https://righto.com

55 nanometers per transistor sounds like a useful number to me.

So does that mean Intel's 10nm products are as good as AMD's 7nm products?

Reply on news.ycombinator.com