How do you propose to design physical gates that would handle ternary logic, in a way that is more efficient than the current boolean implementation?
I think the main obstacle would be the lack of ternary logic designers. VHDL/Verilog could probably be extended/enhanced to support ternary logic, but there would be a learning curve for the designers.
There are companies making specialized chips all the time, so if there were a way to create an efficient ternary circuits, then someone would have made one. For example, AI/neural networks do not care about base (they just need math), and they only need a few types of cells to be useful. But I have not heard of any applications of ternary there.
Intuitively, I assume we'd still want to drive transistors to saturation, so we are not dependent on process parameters. Which means that each transistor still only handles two states, and we need two transistors for each trit. But if we have two transistors, we might as well use them for 2 bits and get even more state out of them.
I'd be curious how modern fpgas do it.
Note that this link is tri-state, not ternary. The "tri-state" is still binary, the third state is to allow attaching multiple outputs to the same bus. Or in the C pseudocode:
Regular binary:
enum { FALSE, TRUE } value;
value = result()
enum { UNKNOWN, FALSE, TRUE } value;
value = result()
enum { FALSE, TRUE } value;
if (enabled())
value = result()
But replicating that with an ATMEL or similar generally requires dancing around with resistor ladders or similar.
For the output side, I guess I you can tri-state the output, but this will by default keep the previous voltage, you will need some resistors to actually emit a voltage outer than "low" or "high". And Z80 cannot even control this on per-pin basis, since it has no integrated GPIOs.
For the input side, I have no idea how would Z80 get more than two states. All the peripherals I know of (like 82C55 GPIO chips) also only provide two input levels as well.
The only way to get 3-state input into a system I can think of are:
- ADC input followed by software thresholding (this will be pretty slow, and works with hundreds of states, not just 3)
- Use external voltage comparators to split a single input wire into multiple input pins. This no long is "single pin" though.
- Some FPGA/CPLDs have multiple banks with changeable input thresholds. This lets you avoid external comparators. You'd still need multiple pins for each input wire.