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Comment by anonymousiam | Hacker News Reader

This may be the next phase of computing to keep Moore's Law on track. (Yes, I know it's not actually a law.) Flash memory has been using multi-state cells for a decade or more. All we need is a new ternary logic family (and FPGA/ASIC foundation library), and some good designers that aren't hung up on using only boolean logic.

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How do you propose to design physical gates that would handle ternary logic, in a way that is more efficient than the current boolean implementation?

Good question. After thinking about it for 30 seconds, I would say add a negative power rail go from there. All gates are analog circuits at the lowest level, so it would not be very difficult to come up a circuit design.

I think the main obstacle would be the lack of ternary logic designers. VHDL/Verilog could probably be extended/enhanced to support ternary logic, but there would be a learning curve for the designers.

I don't think that the problem is with the lack of designers.

There are companies making specialized chips all the time, so if there were a way to create an efficient ternary circuits, then someone would have made one. For example, AI/neural networks do not care about base (they just need math), and they only need a few types of cells to be useful. But I have not heard of any applications of ternary there.

Intuitively, I assume we'd still want to drive transistors to saturation, so we are not dependent on process parameters. Which means that each transistor still only handles two states, and we need two transistors for each trit. But if we have two transistors, we might as well use them for 2 bits and get even more state out of them.

Not claiming it's efficient, but here's a description of how the Z80 does tri-state output: https://baltazarstudios.com/anatomy-z80-gate/

I'd be curious how modern fpgas do it.

Modern FPGAs do it pretty much the same -- there are high and low drivers, and one of them gets activated at a time.

Note that this link is tri-state, not ternary. The "tri-state" is still binary, the third state is to allow attaching multiple outputs to the same bus. Or in the C pseudocode:

Regular binary:

     enum { FALSE, TRUE } value;
     value = result()

Ternary:

     enum { UNKNOWN, FALSE, TRUE } value;
     value = result()

Tri-state (as Z80 and every modern computer does it):

     enum { FALSE, TRUE } value;
     if (enabled())
        value = result()

(the idea is you might have multiple components driving the same "value", and only one of them should be enabled at a time. Bad things happen if more than one is enabled at a time, or none are)

That's helpful, though googling around a bit suggests both the Z80 (and popular peripheral chips) and FPGA/CPLD devices do have non-bus, single pin abstractions that can output and input 3 states with a single pin.

But replicating that with an ATMEL or similar generally requires dancing around with resistor ladders or similar.

Can you tell me more about how can Z80 (or popular peripheral chips) "can output and input 3 states with a single pin"? Or maybe give some web links? I am pretty familiar with that chip, so hearing this surprises me.

For the output side, I guess I you can tri-state the output, but this will by default keep the previous voltage, you will need some resistors to actually emit a voltage outer than "low" or "high". And Z80 cannot even control this on per-pin basis, since it has no integrated GPIOs.

For the input side, I have no idea how would Z80 get more than two states. All the peripherals I know of (like 82C55 GPIO chips) also only provide two input levels as well.

The only way to get 3-state input into a system I can think of are:

- ADC input followed by software thresholding (this will be pretty slow, and works with hundreds of states, not just 3)

- Use external voltage comparators to split a single input wire into multiple input pins. This no long is "single pin" though.

- Some FPGA/CPLDs have multiple banks with changeable input thresholds. This lets you avoid external comparators. You'd still need multiple pins for each input wire.

Apologies, you're right. It was my own misreading bits of code where a chip was inferring its own pin state (1/0/hi-z) based on previous calls or flags and what it should be. Not inferring it externally.

Firstly, how exactly would this work? Does the transistor itself become ternary?

Secondly, Jim Keller paints a fairly convincing picture that (for some definition of Moore's law) there is definitely a long way to go yet.

A transistor is an analog device. Digital logic usually has them operating in either an "on" or "off" state, and this could still be the case if a second power rail was added.

Jim Keller is obviously extremely intelligent, but it's also in his best interest (at least it was at the time when he made his most recent comments about Moore's law) that people think Moore's law is still in full-force.

Why? He was at Intel so wouldn't him saying Moore's law isn't dead expose their process failings even more?

Yet it's still in force. Not scaling quite as quick, but still exponential growth in the number of transistors.

Why stop at ternary?

No good reason I can think of. Flash memory manufacturers began with SLC, but have been evolving to higher and higher cell densities.

https://www.howtogeek.com/444787/multi-layer-ssds-what-are-s...

Also, early computers were not all based on binary. E.g. The ENIAC was base-10. https://en.wikipedia.org/wiki/ENIAC

Nope, ENIAC was binary, it still had bits: https://wikis.olin.edu/ca/doku.php?id=2014:vacuum_tube_sr_la...

What it did not have was base-2 bytes. It's bit encoding algorithm had "prohibited" states to ensure all numbers are in base 10.

But each individual element in the machine only had 2 states, ON or OFF.

Your comment seems to be in conflict with this source: https://www.seas.upenn.edu/~jan/eniacproj.html

Our vocabulary is influenced by modern computers, where we use every possible bit state. The ENIAC does not really has this, so the definitions are ambiguous. For example, if you are talking about SLC flash or SETUN ternary (which actually have multiple voltage levels), then ENIAC is binary, as it is operating on only two voltage levels. But if you are talking about base-2^n math of the modern computers, then ENIAC does not have it either.

In other words, a binary computer will have 2 possible bit states, 2^n possible byte values, and 2^(n*m) possible word values. For example, Z80 will have 2^8 byte values and 2^16 word values.

A ternary computer will have 3 possible bit states, 3^n possible byte values, and (3^n)^m possible word values.

ENIAC has 2 possible bit states, but a byte has only 10 possible values (which means that some combinations of bits do not form a valid byte). And a word has 10^m possible values.

For more details, let's look at "A REPORT ON THE ENIAC (1946)" [0] from 1946. It is pretty interesting.

The data transmission is in unary(!), see section "1.1.3. Representation of Digits by Pulses". There is a wire per byte which can have 2 voltage levels, and number of pulses corresponds to a number transmitted.

The logic is classical binary, see "1.2.1.3. Gate Tube":

> A gate tube emits a negative signal when both of its input grids are brought from a negative cut off voltage to a positive voltage. Thus, a gate tube is used to note the coincidence of two positive signals and hence corresponds to the logical "and".

The data storage is in binary (or at least bi-state?), see section "1.2.2.1. Flip-Flops". Quote:

> A flip-flop consists essentially of a pair of triodes so connected that at any given time only one of the pair can be conducting. When a certain one of the tubes is conducting (and the other is not), the flip-flop is said to be in the normal state; when the other tube is conducting (and the first is not), the flip-flop is in the abnormal state.

The "byte" counters have ten bits (flip-flops), but only one can be on at a time. so the numbers are stored as 0000000001, 0000000010, 0000000100, etc...

https://ftp.arl.army.mil/~mike/comphist/46eniac-report/chap1...

https://www.coursehero.com/file/p5n6do7/The-ENIAC-was-decima...

It would probably make the computer slower due to (further) implementation issues. Going from unary to binary computers provides an exponential speedup (this can be seen by having various kinds of Turing machines emulate each other), but further increases do not help that much.

No efficiency advantage to go more than three:

https://en.wikipedia.org/wiki/Radix_economy

Wow, this is fascinating, thanks for the link.

I just wrote a very detailed comment on this thread on why ternary computers aren't a thing, probably can't be a thing, and thus will probably never become a thing.

You might want to read it: https://news.ycombinator.com/item?id=25618303

"2. By theorem, all bases are equivalent in power with respect to their capabilities of encoding information and processing/computing said information, and binary logic can be used to bootstrap any other multi-valued logic system desirable (goes for ternary logic and 64-bit integer computation alike). Thus, the decision to make a base-3 falls back pretty much entirely on circuit efficiency"

This reminds me of Alan Perlis' famous admonition to "Beware of the Turing tar-pit in which everything is possible but nothing of interest is easy."

There are many programming languages which are Turing complete, and so are interchangeable as far as their computing power goes, but as you know they don't tend to compete on efficiency alone.

People want to use the right tool for the job, and many other considerations come in to play.

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