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Comment by lldbg | Hacker News Reader

We still have ways to go.

The node name (3nm) in this example is pure marketing, there is no feature that is 3nm small on the die(s). Smallest feature size is rather 10-30 nm, and you can (again, side of napkin calculation) squeeze in 100 atoms in that space.

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Is there any rationale at all for the name? Maybe it's about how precisely things like corners can be etched, even if the smallest features are much larger than that?

Don't look for a rationale. See this recent article "The Node Is Nonsense:

https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...

It goes in depth into this topic.

I thought the change in node name was relative to the percent improvement in density, i.e 70% increase in density 5 / 1.7 ~= 3

Was there a point lets say at 130nm when the name of the process was meaningful and if so what component of the gate was at X nm for it to be called a X nm process?

I brought up the first ever 110nm node and it was based on the memory half-cell width in a standard way that we didn’t use because it didn’t functionally scale down to that size anymore, but the lithography equipment could make something that passed Intel’s TEM inspection according to expert analysis. So, from what I understand, not since Intel left the DRAM business.

Problem is that gate design itself changed.

Was that FinFET? And is 3nm gate-all-around?

There was quite a variety of MOSFET before FinFET, it yeah, that was a hard right turn.

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