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Comment by dbbk | Hacker News Reader

Serious question, what is the hypothetical limit of this? 1nm? Can you go lower than that?

We still have ways to go.

The node name (3nm) in this example is pure marketing, there is no feature that is 3nm small on the die(s). Smallest feature size is rather 10-30 nm, and you can (again, side of napkin calculation) squeeze in 100 atoms in that space.

Is there any rationale at all for the name? Maybe it's about how precisely things like corners can be etched, even if the smallest features are much larger than that?

Don't look for a rationale. See this recent article "The Node Is Nonsense:

https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...

It goes in depth into this topic.

I thought the change in node name was relative to the percent improvement in density, i.e 70% increase in density 5 / 1.7 ~= 3

Was there a point lets say at 130nm when the name of the process was meaningful and if so what component of the gate was at X nm for it to be called a X nm process?

I brought up the first ever 110nm node and it was based on the memory half-cell width in a standard way that we didn’t use because it didn’t functionally scale down to that size anymore, but the lithography equipment could make something that passed Intel’s TEM inspection according to expert analysis. So, from what I understand, not since Intel left the DRAM business.

Problem is that gate design itself changed.

Was that FinFET? And is 3nm gate-all-around?

There was quite a variety of MOSFET before FinFET, it yeah, that was a hard right turn.

For quite some time these nanometers is only a name. The only limitation right now is imagination of people working in TSMC and other (also money, I guess).

Here's a video of Jim Keller presenting Intel's share of tricks for a few future generations: https://www.youtube.com/watch?v=oIG9ztQw2Gc

What a great talk, thank you for sharing.

Absolutely. At some point, the electrons in the transistor experience quantum tunneling - i.e. they jump over the gate. Which means it's not a very useful gate anymore...

See this great video about it : https://www.youtube.com/watch?v=67S4IyakRko

There’s nothing special about quantum tunneling versus ordinary conduction. You lower the energy barrier, the probability of crossing the barrier increases exponentially. Think about how GAA works. Makes no sense from the electrostatic perspective, right? All it’s doing is lowering the tunneling barrier from source to drain. The issue with size is the ratio of energy states in the interfaces between materials versus bulk crystal.

Quantum tunneling can happen when no conduction is supposed to be happening which isn't desirable.

On the other hand, when we can master the QFET, quantum tunneling gets turned into a desirable trait with huge benefits.

https://en.wikipedia.org/wiki/QFET

The dirty secret is that you can't really make a transistor much smaller than about 30nm.

The contacted gate pitch (for all intents and purposes this is the 'size' of a transistor) actually only decreased 50% from 28nm to 7nm (from 117nm to 64nm).

According to Jim Keller we still have a very long way to go.

Lex Fridman's podcast interview with him on YouTube is amazing.

If this Forbes article is correct, a nanometer of silicon is about 2 atoms wide. Can't get much smaller than that!

https://www.forbes.com/sites/jimhandy/2011/12/14/how-big-is-...

If you look at the actual measurements of their 3nm process they are not near 3nm. The smallest dimension is nearer to 10x that.

You should read about EUV tech and what ASML does if you are interested on this topic.

even if you can't go lower than 1nm or whatever. three-dimensional integrated circuit, chiplet, improvement in packaging...etc. is pushing semiconductor to better performance.

i don't think you can judge it with Moore's law anymore.

The spacing between silicon atoms is 0.235nm.

An atom is about 0.2nm?

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