TSMC confirms 3nm tech for 2022, could enable epic 80B transistor GPUs | Hacker News Reader

TSMC confirms 3nm tech for 2022, could enable epic 80B transistor GPUs

pcgamer.com

217 pointsChazprime185 comments

> TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon [...]

> TSMC is already producing chips for Apple’s iPhones on its new 5nm node, which is good for 173 million transistors per square millimetre [...]

3nm™: a transistor is 1 / 250e6 = 4e-9 square millimeters, which is sqrt(4e-9) = 63.2 nanometers by nanometers.

5nm™: a transistor is 1 / 173e6 = 5.78e-9 square millimeters, which is sqrt(5.78e-9) = 76.0 by 76.0 nanometers.

So is it reasonable to say that 3nm™ -- compared to 5nm™ -- is closer to 63.2 / 76.0 * 5 (nm™) = ~4.16nm™? Ie. a reduction in feature size of ~17%?

3nm, 5nm, 7nm are all marketing names now since the fabs switched to 3D transistors and not a measure of any exact feature size.

When examined via electron microscope, TSMC's 7nm is just slightly denser than Intel's 14nm++ and not half the size.

“You need to understand that this naming scheme reflects only the process. It’s just the process called 14nm or 7nm … It could be called Intel Blueberry Construction 5 or if it is called AMD Strawberry Process 3, it would give you the same amount of information as having 14nm or 7nm (in the name).”

https://www.time24.news/2020/09/der8auer-compares-tsmcs-7nm-...

They appear to already be acknowledging that fact by using the trademark symbol.

I once read a 350 micron CMOS spec of about 100 pages. Probably just a subset of the spec. Detailing the hundreds of different feature sizes. There is no way you can compact that into a single three digit number only describing the smallest feature size of the gate. I believe it has been regarded as naming/marketing for decades, but the future is not evenly distributed. It used to be indicative of density and denard scaling, but now physics and geometry is more complicated and other factors distorts that relation to such a degree that there is soon more noice than signal in communicating minimum feature size.

They are adding more layers. But nobody said there are no other improvements.

Up to 30% power reduction, up to 70% logic density gain, and up to 15% performance gain is all that matters.

> […] up to 70% logic density gain […]

What does this figure reflect when transistor density has only increased by ~45%?

That's a good point. Maybe that's the product of improved transistor density and power efficiency?

I remember seeing someone saying that some of the improvements AMD had with Zen 3 were due to optimization of their layout, so this could be similar.

>up to 70% logic density gain

The keyword here is logic density. Transistor density could refer to many things, in marketing speaks that normally means SRAM.

Why is logic density greater than e.g. SRAM density?

A better measurement would be million transistors per square milimeter(Mtr/mm2).

So Intel's self reported 44Mtr/mm2 @ 14nm, and 100Mtr/mm2 @ 10nm(but currently 10nm is having problems).

Comparing this to Tsmc's 170Mtr/mm2 @ 7nm and 250Mtr/mm2 @ 5nm - is a pretty valid comparison, I think.

So if anything, a naive 'nm' comparison is actually too favorable to Intel? That's amusing, since I've heard it suggested by Intel fanboys that it was the other way around.

Because your parent got it mixed up.

170 Mtr/mm2 refers to 5nm. TSMC's 7nm is roughly 100 Mtr/mm2 depending which 7nm you are referring to as TSMC has quite a few variants.

So yes, Intel's 10nm is roughly speaking the same as TSMC's 7nm.

Just to give another perspective, by the end of 2020, TSMC would have shipped more 5nm wafers then Intel's 10nm has ever shipped.

3D transistors so cubic milimeter might be better?

The transistors are 3D only in the sense that FinFETs aren't just wires on top of a flat surface of doped silicon. There's still no 3D stacking of one transistor on top of another, and transistor density is still best measured by how much 2D wafer area is occupied by a transistor.

This is very different from the situation for NAND flash memory, where the memory cell array is genuinely 3D and pushing toward hundreds of layers of memory cells, so volumetric measurements are starting to become useful. (However, the horizontal dimensions of various 3D NAND designs are roughly similar, so comparing simply in terms of layer count is a good first approximation of bit density.)

Why aren't we stacking layers of transistors in CPUs? Is it because of heat dissipation issues?

Yes, but another reason is that in flash only tiny amount of cells are active at time. So even with much bigger cells that are required for reliable 3D stacking and more heat production per cell it is still very ok.

we are starting to and beginning to stack transistors on top of each other. It is a heat dissipation issue but it seems like we will be done.

What really matters is energy efficiency (watts/transistor or watts/some computation that utilizes the chip well)

Interesting but what is the Mtr/mm2 for a "true" 3nm transistor? How big is the gap with the marketing names?

You can run the math yourself, but its 111,111 Mtr/mm2.

That's doesn't make sense: TSMC 5nm has 170 Mtr/mm2 so TSMC 5nm is smaller than true 3nm? No way.

111,111 MTr/mm2 >> 170 MTr/mm2

My bad, as a non native English reader I read 111.111 Okay so the gap is a x100 :0

The reality is that not all transistors are the same size. They vary in size depending it's exact purpose and how many other transistors it's driving. To the point where they can be up to macro size visible with the human eye in audio switching equipment for example.

What I don’t understand is why Intel don’t just rename their 7nm process to 2nm... or swap to a more favourable metric name.

They are being honest and should be appraised for doing so.

Intel actually did the opposite, and renamed their second attempt at a 10nm process as "10nm" and dubbed the next iterative refinement of that as "10nm+". They're trying to pretend the failed 10nm process used for Cannonlake never happened.

And to some extent, their continual promises to investors that "10nm" and "7nm" were on track force them to actually ship something under those names.

I had the same question recently, for more details:

https://old.reddit.com/r/ECE/comments/jxb806/how_big_are_tra...

The name is supposed to line up with the smallest feature size. The layout of individual transistors and the layout between transistors is not going to be the same for different processes. What customers actually want is high transistor density and low leakage current. That isn’t how new processes are marketed though. They’re marketed as the smallest feature, which does not have a linear relationship with performance metrics.

Yes, that would be reasonable, for generic transistors. TSMC has started breaking out different 'shrinks' for different things, so 'logic' (which is typically gates and flipflops) has one amount, 'ram' (which is typically a gate and a capacitor) has another different amount, and pin drivers often have still another amount.

TSMC talks about SRAM, not RAM. Those are typically 6 or 8 transistors per bit.

TSMC is killing it. I feel like it would be a strategic investment for the US to take a much larger stake in it and hopefully bring some of that fabrication talent stateside with Intel waning.

TSMC is absolutely killing it, but Samsung is catching up too.

https://techxplore.com/news/2020-11-samsung-chip-wars-tsmc.h...

Still, I think there's a pretty reasonable argument to be made about our dependence on foreign entities for such critical infrastructure. Intel seems to be falling behind pretty quickly.

Wow, 116 billion $ investment. Where this goes? High salaries? Expensive minerals? What makes it as expensive as small country's GDP?

State of the art chip fabs require some of the most advanced technology we've developed, the purest materials we can produce, and the most stringent environments we can maintain.

Exactly. Fabs have air quality restrictions that make surgical rooms look like trash dumpsters, relatively, as far as cleanliness goes.

That's over 10 years, or just over $10B in CAPEX and R&D per year. That sounds a lot, but the company routinely spends $20B-$30B in CAPEX every year. In comparison, Samsung's annual marketing budget (advertising, sales promotion and incentive) easily exceeds that amount.

That being said, Samsung really wants to go beyond memory chips and is serious about the foundry business.

EUV patterning, of which TSMC bit the bullet on early, adds another huge cost to an already crazy expensive manufacturing process.

https://en.wikipedia.org/wiki/EUVL

Hasn’t Samsung been having serious yield issues with their newer processes? I think I remember reading the their 8nm yields were horrible around the time of the RTX 3000 series launch.

The US already has all the most haves.

Most of the IPs are US owned (by Intel, AMD, Texas Instruments, NXP, Apple, Broadcom, Nvidia, Qualcomm, ARM etc). It's just the manufacturing capacity and fabrication facilities.

Intel holds some shares on European based ASML which is the crucial partner for TSMC. The US could even force both ASML and TSMC to not sell products to Huawei even though Huawei was paying a lot of money. The US can effectively kill TSMC anytime.

I don't think mass-scale in-house semiconductor manufacturing is really critical as much as having the tech and the IPs are. Also the US has enough influence on manufacturing, and enough emergency manufacturing capacity already in place. I think public cloud (AWS, GCP, and Azure) is more critical today than mass production semiconductor manufacturing.

ARM isn't yet US owned - at the moment it's still a UK company with a Japansese parent.

What if China were to take over Taiwan and TSMC and stop selling to US companies? Which doesn't seem all that farfetched after what is happening in hong kong. It doesn't really matters who owns the IP if we're talking about nation states that don't have to play by any certain set of copyright rules.

If that happened and the US had to replicate these fabs from scratch that could set computing power in the western world back 5 to 10 years. This seems like a large and growing matter of national security for the US, especially the further behind Intel falls.

This is an important point. TSMC announced earlier this year that they'll be building a foundry in the US[0], but my understanding from what I read at the time is that it's a relative drop in the bucket.

[0] https://www.cnbc.com/2020/05/15/tsmc-to-build-us-chip-factor...

I suspect that this venture will be a failure.

The magic behind TSMC's success, is their huge quantity of semiconductor engineers, that they employ to achieve their yield. It's because the photo-lithography devices from ASML are so finicky, that you need to babysit them.

Which means that you need a lot of engineers. And they must also be relatively cheap. Otherwise, you burn through your budget. Which is also something that Taiwan can provide, since the exchange rate is more favorable for this work.

For the American foundry to work, they must employ a lot of engineers. And engineering labor in the United States is expensive.

Hence, the US foundry may operationally work, but it will be a commercial failure.

> What if China were to take over Taiwan and TSMC?

Let look at an imaginary world where China gets immediate undamaged physical control over all of Taiwan including the TMSC factories, machinery, and staff.

Do you think the machinery will work? Do you think the staff will work? Do you think that TSMC will be able to get the materials it needs for production? Do you think TSMC will be able to run any of the software they need for their operations?

Every step in the manufacturing process is hideously complicated, has huge complicated dependencies, and many extremely sensitive steps that could be sabotaged in very subtle ways.

Here’s a story:

1987--Radioactive contamination of a semiconductor factory

No IBM SER historical review would be complete without mentioning the "Hera problem." During the year 1986, there was an anomalous increase in LSI memory problems. Electronics in early 1987 appeared to have problem rates approaching 20 times higher than predicted. In contrast, identical LSI memories being manufactured in Europe showed no anomalous problems. Because of knowledge of the radioactivity problem with the Intel 2107 RAMs, it was thought that the LSI package probably was at fault, since the IBM chips were mounted on similar ceramic materials. LSI ceramic packages made by IBM in Europe and in the U.S. were exchanged, but the European computer modules (with European chips and U.S. packaging) showed no fails, while the U.S. chips with European packages still failed at a high rate. This indicated that the problem was undoubtedly in the U.S.-manufactured LSI chips. In April 1987, significant design changes had been made to the memory chip with the most problems, a 4Kb bipolar RAM. The newer chip had been given the nickname Hera, and so at an early stage the incident became known as the "Hera problem."

By June 1987, the problem was very serious. A group was organized to investigate the problem. The first breakthrough in understanding occurred with the analysis of "carcasses" from the memory chips (the term carcasses refers to the chips on an LSI wafer which do not work correctly, and are not used but saved in case some problem occurs at a future time). Some of these carcasses were shown to have significant radioactivity.

Six weeks was spent in the manufacturing process lines, looking for radioactivity, and traces were found inside various processing units. However, it could not be determined whether these traces came from the raw materials used, or whether they were transferred from the chips themselves, which might have been contaminated earlier in their processing. Further, it was discovered that radioactive filaments (containing radioactive thorium) were commonly used in some evaporators. A detailed analysis by T. Zabel of some of the "hot" chips revealed that the radioactive contamination came from a single source: Po210 This isotope is found in the uranium decay chain, which contains about twelve different radioactive species. The surprising fact was that Po210 was the only contaminant on the LSI chips, and all the other expected decay-chain elements were missing. Hundreds of chips were analyzed for radioactivity, and Po210 contamination was found going back more than a year. Then it was found that whatever caused the radioactivity problem disappeared on all wafers started after May 22, 1987. After this precise date, all new wafers were free of contamination, except for small amounts which probably were contaminated by other older chips being processed by the same equipment. Since it takes about four months for chips to be manufactured, the pipeline was still full of "hot" chips in July and August 1987. Further sweeps of the manufacturing lines showed trace radioactivity, but the plant was essentially clean. The contamination had appeared in 1985, increased by more than 1000 times until May 22, 1987, and then totally disappeared!

Several months passed, with widespread testing of manufacturing materials and tools, but no radioactive contamination was discovered. All memory chips in the manufacturing lines were spot-screened for radioactivity, but they were clean. The radioactivity reappeared in the manufacturing plant in early December 1987, mildly contaminating several hundred wafers, then disappeared again. A search of all the materials used in the fabrication of these chips found no source of the radioactivity. With further screening, and a lot of luck, a new and unused bottle of nitric acid was identified by J. Hannah as radioactive. One surprising aspect of this discovery was that, of twelve bottles in the single lot of acid, only one was contaminated. Since all screening of materials assumed lot-sized homogeneity, this discovery of a single bad sample in a large lot probably explained why previous scans of the manufacturing line had been negative. The unopened bottle of radioactive nitric acid led investigators back to a supplier's factory, and it was found that the radioactivity was being injected by a bottle-cleaning machine for semiconductor-grade acid bottles. This bottle cleaner used radioactive Po210 material to ionize an air jet which was used to dislodge electrostatic dust inside the bottles after washing. The jets were leaking radioactivity because of a change in the epoxy used to seal the Po210 inside the air jet capsule. Since these jets gave off infrequent and random bursts of radioactivity, only a few bottles out of thousands were contaminated.

Edit: The amounts involved with the above are minuscule. The above really fits in with “The Modern World Has Finally Become Too Complex for Any of Us to Understand” https://news.ycombinator.com/item?id=25277054 — I am imagining all the complicated equipment to detect this type of problem in a modern IC facility (I have a little experience with environmental radiation detection and while the physics seems “simple”, the equipment is not.)

Fascinating read! Thanks for sharing.

The story is an excerpt from:

Ziegler, James F., et al. "IBM experiments in soft fails in computer electronics (1978–1994)." IBM journal of research and development 40.1 (1996): 3-18.

> Do you think the machinery will work? Do you think the staff will work? Do you think that TSMC will be able to get the materials it needs for production? Do you think TSMC will be able to run any of the software they need for their operations?

Yes to all of those questions. Even if it took a year to re-establish dependencies in sourcing of materials, I don't see why they wouldn't be able to do it.

> I don't see why they wouldn't be able to do it

There can easily be plenty of critical knowledge employees who don't like the idea of their homeland now being occupied and would rather migrate to Singapore or Australia or something.

China clearly needs these people, otherwise they would already have a factory of their own going.

Most people at this level have families, and if told that they can keep their jobs/homes, will almost all stay.

The is precisly why the US wouldn't let that happen. TSMC existing in Taiwan means that the US needs to keep Taiwan safe.

Taiwan sees that threat and from my understanding has a scorched-earth policy where all their most valuable industries will be destroyed in the case of an invasion.

At that point, China would have little to gain and lots to lose. Unlike Hong Kong which was handed to them, Taiwan claims to be a sovereign state.

I’d very much like to read more about such a policy. Do you have any recommended reading?

I'd like to read more on that. Can you link sime sources?

> What if China were to take over Taiwan and TSMC

It's highly unlikely that China can take over Taiwan without doing immense damage to the island due to the required military force. So the move might work to hinder the US from benefiting from Taiwanese based operations, but it will be more of a destruction than a takeover.

ARM is not owned by NVIDIA (US). The deal is still going through and is expected to take 16 months for it to be completed assuming no other countries (UK, China, etc.) try to block it before then.

It's a bit premature to assume it's a "done deal".

I'll be surprised if the UK lets it go through.

Given a choice I would rather have the manufacturing facilities. Imagine a war between country A and B, where A has all the intellectual property for making the weapons but none of the factories. B has all the factories but none of the IP. Who would win the war? Obviously B.

But that argument applies to everything we outsource to Asia. There are more critical products during the war time. I'm sure we can live without 3nm processors for a few years if we have to. You just need to have some stockpiles, some emergency manufacturing capacity, and the knowledge to scale up your domestic manufacturing capacity when you don't have a choice.

The problem is IP can be stolen easily and leveraged very quickly.

Hard to steal a plant.

> The US could even force both ASML and TSMC to not sell products to Huawei even though Huawei was paying a lot of money.

I believe that TSMC have already received a ban on selling to Huawei -- https://www.caixinglobal.com/2020-10-16/tsmc-wont-sell-chips...

Well there is a 5nm TSMC fab coming to Arizona, maybe thats the needed lead-in.

https://www.tomshardware.com/news/tsmc-arizona-fab-investmen...

> hopefully bring some of that fabrication talent stateside

Taiwan will never let that happen. Having TSMC's expertise stay where it is is a matter of national security for them, since it gives them a bargaining chip to force the US to come to their aid if the worst happens.

I'm super curious -- how does chip manufacturing yield go with node size?

Do they need to design even more defect-tolerant designs if the density of random environmental contamination stays about constant? (Is that true?) Or do they need the clean rooms, solvents, filtration, etc. to improve just as much with every jump in node size?

I was also wondering, since Apple is not marketing on Ghz and playing the Intel game, how do they deal with variable chip manufacturing yield? Is there a narrow band or minimum chip speed that they'll accept and toss anything performing below? Does the SoC become so physically larger that yields also go down by any significant amount, and any defects at such small sizes become much more troublesome?

> Do they need to design even more defect-tolerant designs if the density of random environmental contamination stays about constant? (Is that true?) Or do they need the clean rooms, solvents, filtration, etc. to improve just as much with every jump in node size?

We are way past that already. Any external contamination, even one stray atom, can cause a defect in any reasonably modern lithography process. There are parts of chips where thicknesses are measured in "monolayers" -- that is, the thickness of the material in that position is one uniform layer of atoms.

Do the photolithography machines operate in vacuum? If not, why not?

Yes, they do, all layering steps additive and subtractive are done in vacuum environments.

If it can be it is in a vacuum. Almost everything is crazier than you think. Many times whenever yields work they just blindly repeat the process - it's a freaking awesome science.

> Almost everything is crazier than you think.

This is a very good rule of thumb about modern leading edge fab technology. Imagine the craziest, most impractical, most expensive things you can come up with for methods to manufacture things. The actual processes used are crazier than that.

For a reference point, just look up how the light source for the EUV steppers work. [0] tl;dr: They are melting tin, dripping the molten tin in droplets of carefully controlled size, shooting those droplets into a vacuum chamber at 70m/s, and then hitting them simultaneously with so many lasers that they are instantly ionized and then emit radiation of the desired wavelength. And they are using this Rube Goldberg-esque contraption as a glorified light bulb. Everything is like that.

[0]: https://www.osa-opn.org/home/articles/volume_29/march_2018/f...

Wow. That's a lot of extra steps compared to what they do with other discharge lamps. I'm not an authority in this area and I don't know proper terminology, so forgive me if I'm mistaken here. There must be some good reasons for all of this. Probably a long list of things to do with optics, power density, and contamination.

Here is a video of a rubidium standard teardown that I like to share. There aren't many places to actually see a discharge lamp.

https://www.youtube.com/watch?v=ymV9LwhD0W0

Is the washing and dissolving with solvents in a vacuum too? Doesn't that cause stuff to boil?

No but they’ll happen in an inert atmosphere, not sure about plasma etching that may require a vacuum chamber similarly to sputtering.

The only steps that absolutely require vacuum are sputtering and ion deposition (doping), depending on the wavelength used vacuum may be used/required for the lithographic exposure too but I’m not sure if it’s actually needed especially since some lithography requires submersion.

That said nothing will be done under normal atmospheric conditions, even the oxide layer will be controlled with specific oxygen rates.

My understanding is that part of the reason AMD went with a chiplet design was to work around this issue.

I wonder if Apple will buy up all the capacity for the new process node again.

Of course. M1 is a huge success and I see more friends of mine buying Apple devices with multiple months of their salaries at this point instead of getting an AMD laptop with more RAM and SSD for half the price.

But would Apple be content with going from 5nm to 3nm nodes so "quickly"? Given that AMD has been able to squeeze out their Zen 2 and 3 IPC without the need to change nodes completely, it could make sense for Apple to do the same.

Yes. The answer to that is yes.

And Apple almost certainly have had the designs in simulation and test/initial sampling already. CPU design isn't an overnight thing.

Apple fundamentally has more units to spread their designs across. Also, for Apple performance per watt is king. Getting 5% better battery life for a phone is massive. For a desktop or even a laptop, it's nice, but maybe not worth paying the premium for TSMCs latest die shrink.

Most Apple users aren't techies.

So a macbook user can now feel he has the best computer and nobody else is even close. Nobody else is being manufactured using that magic. Maybe he'll even brag about that.

How much is that worth to Apple ?

What AMD laptop costs $600 and has more than 16GB of RAM?

In Hungary you get a Macbook Air with 256GB SSD and 8GB RAM (cheapest M1) for $1440:

https://www.alza.hu/macbook-air-m1/18884163.htm

16GB with 1TB SSD is not available, but the official price is $2960:

https://www.apple.com/hu/shop/buy-mac/macbook-pro/13-h%C3%BC...

My girlfriend found a 14'' 16GB 1TB AMD 4000x laptop for $1050 there and loves it (ACER Swift 3)

Looks like VAT in Hungary is as high as 27% (is this the rate that applies in this case? VAT-inclusive pricing disguises this tax.), which accounts for much of the price difference.

Yes, 27% VAT + high tariffs are a toxic combination. At the same time for non Apple products there is maybe some dodging of taxes going on (like a company registered in Slovakia), you never know why a product is relatively cheap there, but you can guess.

I always used argep.hu for pricing computer bits. Dunno who's better

M1 is a good value - I am honestly amazed Apple didn't increase price points given the performance gains relative to the entire field, let alone their previous generation.

Apples pricing can be pretty funny from the outside. They certainly charge a ridiculous amount of money for memory and storage upgrades, on the other side some things are surprisingly cheap. Think of the entry level iPad for example. And now the Mini with the M1 getting cheaper than its predecessor. Short term, Apple could ask any price for the new M1 Macs. However, they have a longer term view with their pricing structure. For sure, they are having way less costs per device, as they don't have to pay the huge sums, Intel asks for their processors. The costs for Apple should be considerably down and they do relay that to the customer.

I suppose it was a wise movement to use that as a way to increase OS market share.

I still see people not liking macOS without even trying it out which is funny but if more people start using it around them, those average joes might start giving them a try which in turn gives Apple profit.

But worse build quality and CPU and laptop power and...

At this point it’s not clear if Apple machines are overpriced in any way; they beat all their competitors at their price point.

Sure, when she asked me about it, I told her to get it, try it for 2 weeks, and bring it back if she doesn't like it.

The value depends on the usage. I wouldn't run photoshop +illustrator together with 256G of SSD and 8GB of RAM (which my girlfriend uses a lot), but M1 is amazing for web browsing, which my friend does mostly.

What exactly do you mean by "build quality"? Do you just mean built from glass and aluminium? (hardly obvious choices for a laptop). IMHO, Apple can hardly claim to be leading in "build quality", what with glued-in batteries, un-repairable designs and keyboard reliability issues that have been ongoing for years.

> Do you just mean built from glass and aluminium? (hardly obvious choices for a laptop).

Aluminium bodies are way less prone to "oilification" (aka visibly shiny areas where one's palm rests), and I have yet to see any Windows laptop where the touchpad is comparable with MBPs in both size and quality (palm tracking, gestures).

> what with glued-in batteries, un-repairable designs and keyboard reliability issues that have been ongoing for years.

Battery replacements are possible even for someone with only moderate experience in hardware work, but I agree with you that the process is more complex than it used to be. Regarding the keyboard: get a 2019 16-inch MBP, it has a keyboard with real keys and a physical esc key.

> un-repairable designs

Quality actually means no need to repair and use it till becomes obsolete. That's why Apple's stuff have drastically higher re-sell value than the competition.

Only repair shops fancy to repair stuff, the rest of us prefer it not breaking down in first place.

LOL. Louis rossman would beg to differ.

no doubt. He made a career of it.

Ancedotally, I have yet to meet a someone whose Macbook didn't break before it became obsolete.

A quality product shouldn't be so fragile to component failures. Bad RAM shouldn't entail an entire motherboard replacement.

I never met someone who's macbook broke down without spilling the punkin spice latte all over it and second hand market is flooded with old macbooks in mint condition.

The base price is reasonable, but the RAM and Storage upgrade costs are extortionate.

That's often the case from other OEMs as well. I just checked a Dell Latitude with a 256GB SSD standard. Upgrading to 512GB costs $146.99, and going from 512GB to 1TB is another $142.72. The retail price for a very good 1TB SSD is about $135, so when you pay for that 1TB upgrade from Dell, you would still be getting ripped off even if they also sent you the 256GB and 512GB drives. For $289 in upgrade pricing, Dell owes you at least a full 2TB of storage.

Sure, but with most other OEMs anyone tech savvy (or really just handy with a screwdriver) can buy the base model and get the upgrades separately.

Except that most people don't want to use Apple products, they're fine on Windows.

If you want build quality you buy thinkpad and not apple.

I got a Thinkpad 3yrs ago to replace by (now 6-yr old) Macbook Pro. The Thinkpad died, while my MBP is still going strong.

> AMD laptop with more RAM and SSD for half the price.

So you're saying a hypothetical laptop with two AMD cpus inside is more powerful than a M1-based MacBook, yet still less expensive.

If TSMC are smart they will reserve some capacity for AMD, in order to keep AMD as a customer. Apple has no alternative, so no reason to give Apple exclusive access (unless Apple pays a ton for it).

Or, use all that Apple money and build more capacity. Perhaps even try to get money out of the US federal government in exchange for an agreement to build new factories in the lower 48.

TSMC has announced they will build a 10nm fab in Arizona. But strategically speaking, Taiwan has an interest in keeping the latest and greatest fabs in Taiwan. It’s an incentive to keep the US invested in their defense.

And a good incentive now that Intel loses ground slowly.

You don't need latest, and greatest process to make chips for missiles.

Sure, but you might need it to keep several trillion dollars of GDP afloat and ensure economic stability, which is a precursor for national security.

> Apple has no alternative, so no reason to give Apple exclusive access

Likely billions of reasons. It's likely Apple pays a significant premium to get that capacity.

AMD might not even mind this arrangement. Apple is essentially funding these die shrinks and AMD benefits down the road.

> AMD might not even mind this arrangement. Apple is essentially funding these die shrinks and AMD benefits down the road.

Agree with that. AMD is doing amazingly well with just architectural improvements for Zen 3, so I’d bet they’re plenty happy to just let everyone else work out the kinks in 5nm before they hop on in a year or so.

Apple is the one company that has proven itself as extremely capable of going more vertical when it is unhappy with its suppliers. This could be a case where if they don’t fulfill apple’s requests, they could lose Apple completely long term.

This.

Nobody thought Apple would make its own CPUs (SoCs, really.)

Apple is going vertical.

Apple is vertical in design (IP, software) not manufacturing.

As far as I know, Apple doesn't manufacture anything. All manufacturing is outsourced. So it isn't likely that they will want to build a fab for several 10's of billions of dollars even thought they probably could.

Apple isn't going to be replacing TSMC. It would take a few hundred billion dollars of investment at best.

Apple has deep enough pockets. They could stomach it.

I'm not convinced the advantage it might or might not conter would be worth hundreds of billions of dollars.

There is absolutely no way Apple would build their own foundry. You are talking about a yearly investment of five to ten billion dollars, not to mention how long it'd take to actually make it production ready.

Technical problems aside, Apple's stakeholders would fire the entire board if they approved something like that.

I don’t think shareholders would be very happy to have that money spent on capex instead of paying dividends.

Apple has not really "bought up all the capacity" it was just PR spin. they had simply booked three months worth while TSMC is still ramping up the 5nm process.

Apple market share is simply not large enough to do that. Yes their numbers are huge, but there are lot more people who cannot or will not buy laptops priced $ 1,000+ than there are ones who are ready to pay that globally.

It’s not just the M1 though. I believe they are going to be if they aren’t already using TSMC for all their chips so iPhone, iPad and Apple Watch if I recall correctly. That’s a lot of capacity.

Ultimately they’re in this huge success mode which is great! They just have to be careful Not to overbuild additional supply and end in a situation where demand tempers for some reason and they are now in a glut

To first approximation, it's not the M1 at all. In terms of silicon area, Apple ships iPhones, with a few other products mixed in. But mostly they just make iPhones.

Android devices outsell the iPhone almost 10 to 1. I'd wager that Qualcomm's 5nm orders will be very close to Apple's current order.

I think Android chips have less die area though (because they have less cache) and many android devices are rather cheap and have SoCs produced on older processes.

Snapdragon 865 is 83.54mm^2 (7nm)

Apple A12 is 83.27mm^2 (7nm)

Apple A13 is 98.48mm^2 (7nm+)

Apple A14 is 88mm^2 (5nm)

Not a very big difference. Remember, Qualcomm's chip includes a modem while Apple's does not (at present). Qualcomm has also been putting a lot of resources into other areas like neural processors. Their upcoming 888 claims 26 TOPS (vs 11 TOPS for Apple)

Cache is a very common misnomer too. A14 has 8MB of shared L2. 888 has 4MB of shared L3 plus 1MB for the X1 core and 0.5MB per each A78 core. It also has 3MB of what they call DSU cache which serves as a kind of general cache for everything on the chip that needs to hit memory. That's actually 1.5MB more total cache than Apple offers.

> will not buy laptops priced $ 1,000+

The iPhone and iPad are using up a lot more of TSMC's capacity than the Mac. Also most sub $1k laptops and lower end phones not getting chips with the latest TSMC silicon in them. They are getting older 14nm Qualcomm, AMD, or Intel CPUs.

EDIT: I previously implied all sub $1k laptops had 14nm CPUs which isn't true.

You say that, but there are certainly Ryzen 7 laptop models around in the sub-$1k range. People like HP put their mid-ranges together with AMD chips on the basis that Intel's were the premium ones.

Now, these models do exist, in theory. I challenge you to find any stock, though, and that's going to hurt AMD.

Agree. My above post was poorly worded.

The 4700U/4500U product lines have been everywhere for the past few months in the US. HP/Dell/Acer all have products sitting on the shelves at best buy, walmart, etc. These are the mid-tier AMD products, but they are extremely well placed when compared with the vast majority of the intel product lines they are sitting next to. In many cases the $600-700 those products are selling for best pretty much all the intel products priced below $1200 or so.

(HP, which I don't recommend, was selling a 4700U based product starting at $400 on black Friday on their web site)

edit: Heck just checked there are loaded Asus ROG G14's in stock at a local retailer for under $1200 (that is 4900HS+RTX 2060). Pretty much one of the fastest laptops out there.

> Intel 7nm is estimated to deliver around 200 to 250 million transistors per square millimetre

> TSMC reckons its 3nm node will pack in somewhere north of 250 million transistors per square millimetre of silicon

Why is a 3nm process would yield the same transistor density as a 7nm one? Is it an error in the article or there is something I do not understand?

From what I understand, it is usually the minimum size rather than any kind of average.

It used to be based on a feature size of logic based transistors, but as node shrinks happened the design of transistors changed, so the number didn’t make sense any more.

Different companies measure different things, and it is a marketing designation now. Intel has tried to be more scientific about their naming, but see where that got them.

Clock speeds became similar by the 90s at least since things like instructions per clock and instruction level parallelism can make lower clock speed chips faster than “faster” chips on most code.

Ridiculous really that we now have it as a metric. Transistor count is more sensible, but even that is just a very indirect and approximative measure of performance.

But yes, it is shown again that they should have lied. Just don't do it too much on sensitive topics like emissions...

There probably isn't that much room for improvement anymore since we reach atomic magnitudes.

How has that been shown? Intel's problem isn't the process naming but the lack of results.

Intel could call it whatever they want but they've been stagnating, and that's why they are failing. Its not even that they're stagnating that's the problem, its that the rest of the industry isn't.

Yes, if Apple doesn't take all the available production slots.

Could Apple acquire TSMC or is it state owned?

Regulators across the globe would flat-out say no.

Not trying to stir the pot but genuine question - why would national states not approve this?

Samsung (another phone manufacturer like Apple) has it's own Fab.

And regardless of Intel latest troubles, they are still the dominant fab for non-mobile devices (desktop/laptop/server)

The EU is already investigating Apple as a monopoly. There have been similar vibes from the US. They would see a TSMC purchase as a big monopoly play and squash it.

The theory is that at a certain point, vertical integration is so extensive that you are keeping all the profits along the entire chain and nobody can compete on price. That's a very bad place for government-enforced monopolies like Apple (standing on the back of government-enforced patent and copyright monopolies).

Taiwan will never let TSMC go as long as it's a national treasure like it currently is. I think for a similar reason the UK will buck the Nvidia buyout of ARM

They could still buy all the top talent.

> TSMC is promising at least 250 million transistors per square millimetre for its 3nm node, the reality may turn out nearer 300 million. [...]

> TSMC is already producing [...] its new 5nm node, which is good for 173 million transistors per square millimetre. [...]

> Intel 7nm is estimated to deliver around 200 to 250 million transistors per square millimetre. So falls somewhere in between TSMC’s 5nm and 7nm nodes for density.

If my math is correct, Intel 7nm could be as good as TSMC 3nm for density - it definitely looks better than 5nm. I also believe this will be the first EUV node for Intel, so that would make sense that it's competing more with TSMC's EUV powered nodes.

I like how the article starts with "Monster chip foundry TSMC..."

The M3 processors are going to be sooooo fast. Can’t wait.

Few more generations, and we will see 1BT per mm².

Few more generations with the new Moore's law, means a decade?

Give that full generational gains are definitely slowing, yes, but there is no "iron wall" yet for squeezing a 4 fold gain.

Existing fin/gaa fets can get at least 2 times smaller themselves in both dimensions. 20nm gate length does not look impossible.

Device spacing can get smaller with existing tech, and trench to wall move will add to that.

Metal is actually the biggest worry from what I heard. Lab scale demos for metal capable of 1BT/mm² were done long ago, but contact, and line defect rates are still unworkable, and arise from very fundamental metal deposition physics issues. A completely new approach to building middle end, and M0 may be needed.

Does anyone know any details about the actual types of 3D stacking and other techniques that are going into this "3nm"?

TSMC's 3nm will still be FinFETs rather than any of the more 3D-ish transistor designs: https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...

Other "3D stacking" tech you may have been hearing about is packaging tech that isn't really tied to particular fab nodes—and that's one of the main motivations for advanced 3D packaging: you don't need to make all your chiplets on the same process.

Serious question, what is the hypothetical limit of this? 1nm? Can you go lower than that?

The spacing between silicon atoms is 0.235nm.

For quite some time these nanometers is only a name. The only limitation right now is imagination of people working in TSMC and other (also money, I guess).

Here's a video of Jim Keller presenting Intel's share of tricks for a few future generations: https://www.youtube.com/watch?v=oIG9ztQw2Gc

What a great talk, thank you for sharing.

We still have ways to go.

The node name (3nm) in this example is pure marketing, there is no feature that is 3nm small on the die(s). Smallest feature size is rather 10-30 nm, and you can (again, side of napkin calculation) squeeze in 100 atoms in that space.

Is there any rationale at all for the name? Maybe it's about how precisely things like corners can be etched, even if the smallest features are much larger than that?

Don't look for a rationale. See this recent article "The Node Is Nonsense:

https://read.nxtbook.com/ieee/spectrum/spectrum_na_august_20...

It goes in depth into this topic.

I thought the change in node name was relative to the percent improvement in density, i.e 70% increase in density 5 / 1.7 ~= 3

Was there a point lets say at 130nm when the name of the process was meaningful and if so what component of the gate was at X nm for it to be called a X nm process?

Problem is that gate design itself changed.

Was that FinFET? And is 3nm gate-all-around?

There was quite a variety of MOSFET before FinFET, it yeah, that was a hard right turn.

I brought up the first ever 110nm node and it was based on the memory half-cell width in a standard way that we didn’t use because it didn’t functionally scale down to that size anymore, but the lithography equipment could make something that passed Intel’s TEM inspection according to expert analysis. So, from what I understand, not since Intel left the DRAM business.

If this Forbes article is correct, a nanometer of silicon is about 2 atoms wide. Can't get much smaller than that!

https://www.forbes.com/sites/jimhandy/2011/12/14/how-big-is-...

If you look at the actual measurements of their 3nm process they are not near 3nm. The smallest dimension is nearer to 10x that.

According to Jim Keller we still have a very long way to go.

Lex Fridman's podcast interview with him on YouTube is amazing.

Absolutely. At some point, the electrons in the transistor experience quantum tunneling - i.e. they jump over the gate. Which means it's not a very useful gate anymore...

See this great video about it : https://www.youtube.com/watch?v=67S4IyakRko

There’s nothing special about quantum tunneling versus ordinary conduction. You lower the energy barrier, the probability of crossing the barrier increases exponentially. Think about how GAA works. Makes no sense from the electrostatic perspective, right? All it’s doing is lowering the tunneling barrier from source to drain. The issue with size is the ratio of energy states in the interfaces between materials versus bulk crystal.

Quantum tunneling can happen when no conduction is supposed to be happening which isn't desirable.

On the other hand, when we can master the QFET, quantum tunneling gets turned into a desirable trait with huge benefits.

https://en.wikipedia.org/wiki/QFET

The dirty secret is that you can't really make a transistor much smaller than about 30nm.

The contacted gate pitch (for all intents and purposes this is the 'size' of a transistor) actually only decreased 50% from 28nm to 7nm (from 117nm to 64nm).

You should read about EUV tech and what ASML does if you are interested on this topic.

even if you can't go lower than 1nm or whatever. three-dimensional integrated circuit, chiplet, improvement in packaging...etc. is pushing semiconductor to better performance.

i don't think you can judge it with Moore's law anymore.

An atom is about 0.2nm?

Small enough for all kind of quantum shenanigans going on.

This has been the case for a long time. One of my first jobs was in a fab computing these effects of a new process. That was in 1992.

Mind you, this is not 3nm as in physics, rather 3nm™ as in marketing.

I guarantee you that Apple is already planning 3nm Apple Silicon while everybody else is just getting their 5nm shit in one sock.

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