Every layer in the storage hierarchy is "just a cache" in front the layer below it, so the naming is somewhat arbitrary. L1/L2/L3 caches are transparent from the perspective of the processor - it only sees a change in access times to main memory.

Any advancement in the storage hierarchy means reducing latency at one level or increasing the amount of memory at that level.

Most caches would use SRAM instead of DRAM, but the technology used doesn't define its role. Microcontrollers often have only embedded SRAM, serving as main memory.

Don’t most processors use on-chip SRAM for their cache, which is faster than DRAM?