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Comment by mmastrac | Hacker News Reader

I'm glad to see some real-world individuals testing this. Will be interesting to see a "post-mortem" on why the M1 has done so well, and where the limits will be in the future (ie: how far can you get with DRAM-on-die?)

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In the M1 processor, DRAM is on-package, but not on die. (Even large eDRAMs sharing a die with logic don't currently reach to gigabytes.) How far can DRAM-on-package go? NVidia just released a GPU with 96 GB of HBM on package (80 GB enabled, 16 GB disabled for yield reasons), with 30x the bandwidth (!!!) of the M1 processor. This wouldn't be a low power or low cost solution, but for something like a future generation Mac Pro, it gives a good intuition for how far you can go with today's technology.

Perhaps it's sonething like the following: Say for instance, it cost intel $50 for a piece of silicon and sells it to apple for $300. In apples designs, they could incorporate Nearly any cost of silicon and wouldn't affect The built sales price, because it's fairly decoupled from what they charge?

I'm going to go with a combination of the 5nm feature size, simplified instruction set, an architecture that's low-power by default so it doesn't need to be throttled for heat/power, and the use of many types of specialized cores to better match workloads with cpu power. It's a modern architecture in the way that x86 just isn't as a 40-year-old architecture that has to maintain backwards compatibility.

Someone on that thread was saying that the M1 may be using on-chip DRAM as L2/L3 cache. Not sure how true that is.

Don’t most processors use on-chip SRAM for their cache, which is faster than DRAM?

Yes. The best-known exception is IBM's recent(-ish) power processors, which use large eDRAM as a last-level cache. As far as I know, there's no widespread use of eDRAM on processors smaller than 14 nm.

Every layer in the storage hierarchy is "just a cache" in front the layer below it, so the naming is somewhat arbitrary. L1/L2/L3 caches are transparent from the perspective of the processor - it only sees a change in access times to main memory.

Any advancement in the storage hierarchy means reducing latency at one level or increasing the amount of memory at that level.

Most caches would use SRAM instead of DRAM, but the technology used doesn't define its role. Microcontrollers often have only embedded SRAM, serving as main memory.

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