They way modern CPU design works is that the development team maintains a cycle-accurate software model of the CPU. Changes can be made to the pipeline and memory system, those changes simulated against a real workload, and results reported without ever laying a single transistor. These models are part of the secret sauce to figuring out how to eek out 19% IPC. Yes the simulations are slow. But you can get a lot of value out of 50k or 100k simulated clock cycles.