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They way modern CPU design works is that the development team maintains a cycle-accurate software model of the CPU. Changes can be made to the pipeline and memory system, those changes simulated against a real workload, and results reported without ever laying a single transistor. These models are part of the secret sauce to figuring out how to eek out 19% IPC. Yes the simulations are slow. But you can get a lot of value out of 50k or 100k simulated clock cycles.

It's too expensive to fab test chips so it's all done using cycle-accurate simulation software like SimpleScalar or gem5 and later using FPGA-based emulation like Palladium/ZeBu.

You can run emulations. When I was at NVIDIA almost 10 years ago, they were number 1 user of electricity in Santa Clara, by a big margin, because of their server farm that was used to emulate chips.

Simulations, not emulations!