The point is that there is nothing at all special about cache vs any other kind of memory. There are purely practical distinctions made according to relative timing vs bus cycles and, at times, interrupt latency and head-arm settling time, that dictate the mechanism for faulting in misses. All these times have varied by many orders of magnitude over the years without producing any fundamental change in the principles involved. It's all just memory hierarchy, and has been for fully seven decades, since the very beginning.

It takes a very small time window, and very limited historical awareness, to see Ln, for any n, as indicating anything special. In this case, it indicates what we have lately called "RAM" will now be called "L4" -- just as what was so recently RAM is now L3 -- as persistent phase-change memory moves into the place lately occupied by disks and, more recently, SSDs, and the distinction between "RAM" and "storage" gets fuzzy once again.

Even persistence across power loss has phased in and out, over the decades. The slowest memory happens to now be both random-access and persistent, again, and pretty darn fast this time.