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Comment by p1esk | Hacker News Reader

Intel is still ahead of them, right? Last I’ve heard they are moving pretty aggressively on their “7nm”, which is supposed to be at least as good as TSMC’s “5nm”.

Compare min metal pitch for Intel’s “10nm” (36nm) and TSMC’s “7nm” (40nm) [1]

[1] https://en.wikichip.org/wiki/10_nm_lithography_process

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They've yet to master their own 10nm process let alone 7nm. I don't doubt their processes outdo the competitors on actual die shrinkage but they've been having a hell of a time of it.

From what I understand they are not really comparable like that. It’s like clock speed, there are a lot of games that can be played, and X 10nm can be much better than Y 7nm.

The problem with 10nm is that they were too ambitious and tried to do it without EUV. 7nm is being developed by a different team and does use EUV so it shouldn't suffer from the same delays.

What does it mean to be ahead in 7nm when you are years behind in getting your 10nm process into acceptable yielding mass production?

I don’t see why they can’t be both behind on “10nm” and ahead on “7nm”.

Yes, they are substantially different processes.

True, but they seem to have been ahead on 10nm until they weren't, which calls into question claims about 7nm.

Then there's the question of why they aren't skipping 10nm if 7nm is so ahead.

And theres the question of why they can't 'scale up' their 7nm to do 10nm.

Presumably 10nm is cheaper to produce, so they can use that to make lower-end processors.

There are two technologies used in etching, UV and EUV. UV was designed for nodes upto 40 nm (approx). EUV can be used with accuracy of 13nm. EUV has been under development for more than a decade in several firms, so companies used several trickes to make use of UV for lower sizes. 10nm is the extreme end of it (I guess). For EUV this is standard range. It should work without any issues until 5nm and then special tricks would be used to make the pitch smaller.

So manufacturing 10n, with UV is much harder than manufacturing 7nm with EUV (although it is more expensive).

Yup, back in 2003 I was doing experimental work on creating better EUV mirrors and the amount of reflection achieved was way too low to support any machine with a design similar to UV machines. You needed either a (much) higher intensity source or fewer mirrors.

I've been out of that loop for a while, so I don't know how the design of the EUV machines turned out.

AFAIK, some (less than?) 2% of energy put into the EUV source ends up at the wafer. The EUV-source has been the biggest struggle for ASML from what I gathered in media.

Apparently, tiny droplets of tin are created by spinning some disk(s) and then those droplets are zapped with with a laser before they emit EUV. Those machines are crazy complex.

UV is under 1%, and EUV is under .01%

But don't TSMC use UV right now for their process? If so, UV vs EUV can't be the only reason for the mess they've gotten themselves in.

I don't think that Intel is ahead of them. TSMC already started risk production of 5nm chips and plans to start high-volume manufacturing in 2020[0]. According to Intel roadmap they plan to launch 7nm product in 2021 (GPU)[1].

[0] https://www.anandtech.com/show/14175/tsmcs-5nm-euv-process-t...

[1] https://www.anandtech.com/show/14312/intel-process-technolog...

Although "5nm" and "7nm" look like physical measurements, they aren't; all they are is marketing labels, and the only thing you can be somewhat confident of is that if a single company has one process they call "5nm" and one they call "7nm" then the "5nm" one probably has physically smaller features and greater density of components on chip.

And although "2020" and "2021" look like actual dates, they aren't; all they are is marketing labels, because saying you're going to do something in 2020 is cheap.

So what we know is that TSMC say they are going to begin volume manufacturing of "5nm" chips in "2020" (reality: at some unknown date they will be making large quantities of chips on a process to which they have found it convenient to attach the label "5nm"), and that Intel say they are going to launch "7nm" chips in "2021" (reality: at some unknown date they will be making unknown quantities of chips on a process to which they have found it convenient to attach the label "7nm").

Whether TSMC's "2020" is really earlier than Intel's "2021", and whether TSCM's "5nm" is really denser than Intel's "7nm", who knows?

(I'd guess TSMC are in fact ahead, but this isn't a field where you want to be trusting manufacturers' announcements much.)

For what it's worth, the presentation we got from our vendor was 2020 for first 5nm silicon from TSMC.

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