> There are fewer foundries to choose from at the most advanced nodes
To the effect, only two. It is surprising just how fast it has turned into a duopoly.
Samsung and TSMC are now the Airbus and Boeing of semiconductor industry
To the effect, only two. It is surprising just how fast it has turned into a duopoly.
Samsung and TSMC are now the Airbus and Boeing of semiconductor industry
At these scales, very few players can afford to play, even if a breakthrough could net you a very comfortable position for many years.
Thinking about it naively, I can guess at a few possibilities:
- it's highly labor-intensive
- it requires highly specialized skills that command incredibly high prices on the labor market
- it requires lots of prototyping iterations that require expensive materials
- the prototypes are produced on machinery with high opportunity costs
- IP licensing costs
I'm wondering if one of these in particular is the dominant cause, or if it's all of them in conjunction, or if there are other major factors I'm not thinking of.
Also, figuring out how to maximize yields to an acceptable level must be a lot of experimentation.
I think those design costs are nonsensical. There are major projects done by groups of 100 or fewer engineers. A really unique design can cost that much, but a licensed design built.on standard cells is less. That is how rocketchip, RiscV, and others get by. As an approximation, every M$ is 2 engineer years. A 100M$ design is...200 engineer years. With an ARM license and other IP, that is likely manageable.
There is a large infrastructure of design tools that keep design costs constrained per design. Fab costs are not so easily limited....
- EUV comes from a plasma of metal created in a vacuum chamber.
- the plasma is created by concentrating a beam of light on a tiny pellet of molten metal
- that beam of light is a 25kw laser, which is borderline weapons-grade. To the point that countries hesitate to even allow it to be imported.
- the laser must be pulsed precisely to vaporize the metal as its flying through the chamber
- residue from the metal vapor quickly builds up and deteriorates the process
getting this stuff to work requires armies of engineers and scientists. the machines themselves are the size of a tour bus.
Compare min metal pitch for Intel’s “10nm” (36nm) and TSMC’s “7nm” (40nm) [1]
Then there's the question of why they aren't skipping 10nm if 7nm is so ahead.
And theres the question of why they can't 'scale up' their 7nm to do 10nm.
So manufacturing 10n, with UV is much harder than manufacturing 7nm with EUV (although it is more expensive).
I've been out of that loop for a while, so I don't know how the design of the EUV machines turned out.
Apparently, tiny droplets of tin are created by spinning some disk(s) and then those droplets are zapped with with a laser before they emit EUV. Those machines are crazy complex.
[0] https://www.anandtech.com/show/14175/tsmcs-5nm-euv-process-t...
[1] https://www.anandtech.com/show/14312/intel-process-technolog...
And although "2020" and "2021" look like actual dates, they aren't; all they are is marketing labels, because saying you're going to do something in 2020 is cheap.
So what we know is that TSMC say they are going to begin volume manufacturing of "5nm" chips in "2020" (reality: at some unknown date they will be making large quantities of chips on a process to which they have found it convenient to attach the label "5nm"), and that Intel say they are going to launch "7nm" chips in "2021" (reality: at some unknown date they will be making unknown quantities of chips on a process to which they have found it convenient to attach the label "7nm").
Whether TSMC's "2020" is really earlier than Intel's "2021", and whether TSCM's "5nm" is really denser than Intel's "7nm", who knows?
(I'd guess TSMC are in fact ahead, but this isn't a field where you want to be trusting manufacturers' announcements much.)
Then what is Intel?