5nm vs. 3nm | Hacker News Reader

5nm vs. 3nm

semiengineering.com

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I didn't realize Samsung was offering a 5nm process to customers; this means that TSMC is not the only 5nm foundry out there, as I thought it would be when GlobalFoundries canceled their 5nm R&D program. And it sounds like competition might keep process shrink alive for at least one more node, down to 3nm, although there's a good chance that either Samsung or TSMC will have to bow out at that point.

Since Dennard scaling ended about 15 years ago, these new devices will probably run hotter, adding to the dark-silicon, eh, let's call it a situation. It's a problem from the traditional point of view where you expect to be able to use all your hardware all the time, but maybe it's an opportunity if you see it as a chance to handle burstier computational loads or to pack a greater diversity of specialized cores onto a chip. But of course that increases both design costs and the complexity of programming the device once it's been fabbed.

The impending collapse of Moore's Law has thus been delayed for two or three years, or softened anyway, but the appetite for computation due to deep learning continues unabated. Since scaling Jack Kilby's planar process down is becoming increasingly uneconomic, this would be a good time for a non-planar process to emerge — a trillion squares occupies a one-million by one-million area, while a trillion voxels is only ten thousand by ten thousand by ten thousand, a scale a hundred times larger and therefore less demanding on your fabrication processes. You'll probably need some plumbing in there for coolant. I don't know of anybody working on this, surprisingly.

What about https://nanoheat.stanford.edu/sites/default/files/publicatio... ?

No commercial projects that I know of, though.

So it turns out that microfluidics isn't really the best solution since you more or less need cooling channels between the layers and microfluidics is too big for that (without extreme pressure drops) for truly useful 3D integration.

Source: I work on 3D chips for deep learning

I agree with you, and wonder why it's so hard to make chips 3D, but have a quibble. Jack Kilby's integrated circuit wasn't planar. Gold wires connected each part. Jean Hoerni at Fairchild is the inventor of the fully planar process. http://aneeshpthankachan.blogspot.com/2014/01/era-of-integra...

to make a 2-D (1 layer) chip you need N mask/etch steps with probability P of failure, to make a slightly 3-D, 2 layer chip you need 2N steps and have a probability of P^2 of failure etc

Note that exponential term for probability of failure - 10000 layers means 10000N etch steps but P^10000 turns a 99.9% yield for 1 layer device into a .004% yield for a 3d 10k layer device .....

note: by 'layer' here I'm including all the metal/poly/passivization layers in a current device - also after each layer you'd have to leave space to plane the finished layer flat as a base for the next - which means insulation between them deep enough to fill in all the gaps in the previous layer plus vias - and as others mention some way to pull heat out of the core of what has historically been called a "hairy smoking golf-ball" CPU

If every step either worked perfectly or didn't work at all, that would be very convincing. But isn't the reality that defects are localized and that the rate of defects is more or less proportional to the amount of stuff you're making?

If you have a certain probability of failure in each transistor (I know, I know, ICs don't consist entirely of transistors, but let's simplify) then making more transistors by stacking layers needn't lead to more failures than making more transistors by making larger-area 2D chips.

Existing fabrication methods already produce some failures. In at least some cases, the way that's dealt with is to make the hardware able to cope with some bits not working, and then e.g. you can turn an 8-core chip with a defect in one core into a 6-core chip that you sell for less money, or a memory device with one block of memory not working into ... exactly the same as all your other devices because you already budgeted for a couple of blocks not working.

So I think the p^n issue is illusory: n doesn't get larger just because you're making your device in 3D, it gets larger because your device has more stuff in it, so the issue is large devices not 3D ones, and there are already known ways to deal with the fact that large devices often have defects. 3D devices might well have a higher failure rate per unit of stuff on them because the processes would be more complicated, because there are connections in more directions, because of thermal issues, etc., but that's a matter of increasing p, not of increasing n.

But isn't the reality that defects are localized and that the rate of defects is more or less proportional to the amount of stuff you're making?

Not all defects are local. Sometimes you have to throw out the entire wafer. The rate and kind of defects is specific to each step in the process and there are many steps.

To make a wafer of modern semiconductor devices is a process that takes up to 4 months! If you double the number of layers you're already looking at 8 months and without some improvement in the reliability of each step you definitely are squaring the probability of producing a defect free device.

Making a device with ten thousand layers would require completely different technology, since we can't wait 40,000 months for the chips to arrive.

Mostly people don't make fault tolerant hardware - instead we do die level tests (first on bare dies and then in depth on packaged ones) and toss the bad dies.

However we're talking here about building 3D stacked devices instead, to get speed we're going to build cubic CPUs (to reduce speed of light delays), not piles of single layer square CPUs, maybe 100 layers deep - certainly we can disable bad CPUs but that still means we're getting an error rate at P^100

Thank you for the correction!

I think one of the particularly interesting aspects of Machine learning is that the research into it has been focused on parallelism and partitioning from day 1. The result of this is that those work loads are particularly well suited to just scaling to more chips. It may be that we can continue our computational climb for a while longer simply by scaling out in a way that consumer driven products really weren't able to do.

> It may be that we can continue our computational climb for a while longer

I have a random question. Imagine this hypothetical scenario: semiconductor manufacturing comes to a halt completely, and new physics and technology is still decades ahead, can we further improve the practical performance of general computation by innovation alone?

I imagine, instead of riding on the train of Moore's Law, more resources would be invested to design optimization and R&D of new architectures, e.g. faster FPU, faster pipeline, etc.

Also, previously discarded and ignored ideas may be implemented again, and delivers some real advancement. While exponential growth is not possible, at least linear scaling should be the case. For example, computers without clocks. Based on this comment on HN, https://news.ycombinator.com/item?id=19554248, one major obstacle of clockless chip is the entire VLSI toolchain is designed and optimized for synchronous logic, and this can be changed if the industry invest some serious resources. Another example comes to my mind is high-level programming based on hardware, e.g. Lisp machine.

Does my imagination make any sense?

>can we further improve the practical performance of general computation by innovation alone?

we can improve the performance of average programs by a factor of ~100x simply by more careful software engineering. Don't use python or javascript, optimize code for cpu cache hits, use more cores effectively, etc.

However games, maybe only 2x if anything.

I was referring to the computational capabilities that hardware can provide, not the performance of an average program. The parent article talks about semiconductor manufacturing, you can save your rants on inefficient and useless programs for another HN article.

It's not a 'rant'. This is exactly why speeding up CPUs is more difficult, even with billions of transistors. People expect to write whatever they want and have it run faster. 1% of the transistors in a CPU are actually running instructions, the other 99% are trying to keep it busy.

> gameswithgo: Don't use python or javascript

It is clearly a rant to me! Don't get me wrong, I'm not a huge fan of JavaScript, but discussing about useless programs is simply not what I'm asking here. I'm not interested in how Google Chrome can be 1000% faster.

> People expect to write whatever they want and have it run faster. 1% of the transistors in a CPU are actually running instructions, the other 99% are trying to keep it busy.

I agree, now, your perspective makes the talk on software interesting.

Recently I've seen an article C Is Not a Low-level Language (https://queue.acm.org/detail.cfm?id=3212479), in the article the author argued that the in-order, synchronous, sequential execution model from the PDP-11 heyday is outdated. However vast majority of programs (i.e. C programs) are still written based on this model, so a CPU must use a lot of resources to dispatch these sequential code and introduce countless transparent optimizations (e.g. ILP), to make existing sequential code faster, on the other hand, the compilers are becoming monsters because they must be as intelligent as possible to understand the algorithms in a program and rewrite them automatically for optimum performance on a modern CPU. As a result of this disparity, the capabilities of what the hardware can actually provide is often underutilized.

The author purposes that we should try discarding the PDP-11's classical "in-order, synchronous" view of a program, and try developing new programming languages and models that designed with the capabilities of modern hardware in mind, such as low-level parallelism to eliminates this disparity. So the CPUs can focus on what they are good at with less overhead of dispatching the instructions.

Personal attacks will get you banned here, regardless of how wrong or off topic some other comment is. Would you mind reviewing https://news.ycombinator.com/newsguidelines.html and using this site as intended? We'd appreciate it.

I'd guess the downvotes are for exaggeration.

Your basic point is correct. We have actually got 20%+ of speed ups in the last 30 years from better algorithms; not just better hardware.

Many programs are I/O limited and wouldn't see 100x from more effective CPU use (eg., Word).

Others need complete re-writes (eg., browsers) and are typically heavily optimized already.

I'd say we could squeeze another generation of Moore's Law just from software design; and another still from algorithm research.

For many classes of algorithms, the speed-up is actually better than Moore's Law.

I don't think it's really an exaggeration to say that optimization of the programs can lead to 100x performance improvements. Sorting algorithms, for instance, improved dramatically from the first computer algorithms in the early 50s (yay Bubblesort) to QuickSort in the 1960s to newer algorithms in the 1980s/90s like Melsort, and even algorithms being written today, like Neatsort: https://arxiv.org/abs/1407.6183

And the thing about algorithms is that for certain problems and large n, they can quickly blow up. Something with just a slightly better big-O could easily mean a 100x better performance at large n.

Well, specific tasks in some programmes are sensitive to these improvements. But since only a fraction of their run time is typically spent in them, the overall improvement wouldnt be 100x.

Occasionally this is true, but often it is not; see the examples in my comment above.

Radix sort predates the 1950s (perhaps it dates from the 1890 US census?), and mergesort (linearithmic, like quicksort) dates from at least the 1950s, if not earlier. I'm not sure when the linear-time variants of radix sort were discovered; it might have been later.

I agree that many problems have experienced super-Moorean algorithmic speedups, but the examples I'd point to might be solving large linear systems (successive over-relaxation), integer factorization, suffix-array computation, and all kinds of search problems, especially including SAT and SMT, rather than sorting of records.

Thank you for providing better examples. I'm not a computer scientist but a physicist.

Of course with optimization the question is always is it worth it. Make Word 1000% faster and it won't make a difference to me as most of the time word is waiting for me to press the next key. Of course this is a reflection of me: I don't use Word much and when I do I'm not using even 2% of what it can do. I'm sure Microsoft knows of areas that if they could improve it would make a difference to power users.

In my average view, Knuth was wrong about optimization. Not technically, but because the vast majority of people writing software took "premature optimization is the root of all evil" to be "optimization is the root of all evil."

I have a long list of encountering software doing things like reading a billions of rows with getline() in C++. That can be a problem [1]. It doesn't matter how good a heapsort is if it's blocked on some architectural primitive and we'd do better to teach to that optimization in CS 101 than sorting.

1. https://lemire.me/blog/2019/06/18/how-fast-is-getline-in-c/

It depends on what you are doing... Modern desktop, and most mobile devices are just fine running CRUD apps written in JS. Same goes for a lot of server processes. That's not to say anyone should be using it for intense algorithmic processes. A lot of what is currently in Python for ML will likely move on to another language, or we may see better AOT and other optimizations for Python itself.

As with all things, it depends on what your needs are and what you are doing. Modern hardware is pretty damned good, and most apps don't need more than what we already have. Or have had for a decade or more at this point.

I've thought this way for a while. Once (if) we start feeling the diminishing returns in transistor scaling, there will be more incentive in the computer architecture side to experiment with the relatively fixed transistor budget that we have.

Yes almost certainly we can keep speeding things up, just a lot more slowly than we are speeding things up right now. There's a lot of room for improvements in more specialized single-purpose hardware, more different sorts of cores tuned for different workloads, and academia has a lot of ideas for algorithmic improvements too. But don't expect these to provide the same rapid increase in capabilities that we've seen with transistors shrinking.

Eventually we'll have nanotube transistor or photonic or spintronic or nano-electro-mechanical or quantum computers. There are firm physical laws saying what the limits of efficient computation are and we haven't reached them yet.

ML's suitability for parallelism mostly comes from the fact that bigger models/state spaces tend to be more powerful. In cases where there no benefit in scaling the problem horizontally, you probably won't have much luck scaling the implementation horizontally either.

For those that are interested, I was able to attend a talk by the guy that started Graphcore. His experienced approach to customized chip design for ML/AI is a really great thing to tap into. Some of the themes were: maximize power usage as its a limiting compute factor, remove off-chip memory, and scale horizontally at the individual processor level rather than "sharing resources across cores".

https://www.graphcore.ai/

> but the appetite for computation due to deep learning continues unabated

Why don't we move to analog computing for DL? This application seems well suited for it.

I tend to assume (not an expert or insider) that if Intel can’t stay in the process race on its own dime it will end up staying in at Uncle Sam’s expense in one way or another. Partly because China’s almost sure to continue its own efforts while TSMC is also always at risk of a hostile takeover by the PLA.

TSMC is not based in China.

Depends who you ask.

And on how far they might be willing to go to assert their point of view. Which was very much my point.

I'm fairly certain that @leoc was alluding to a "hostile takeover" of TSMC being part of a hostile takeover of Taiwan.

I am skeptical that the Trump Administration that imposed the Huawei sanctions is so competent at high-technology industrial policy that it will guarantee Intel's success in this way. Also, I don't think the missing ingredient is so much expense as it is knowledge, though quite possibly the NSA could translate that knowledge from Chinese or Korean and supply it to Intel.

None of those are offering 5nm right now. There are only 7nm foundries out there, the article says they are perfecting their 5nm processes for commercialization, what means there are some months (maybe years) yet until we see them.

Also, Moore's Law is dead by years now. Not only process improvement became subexponential and much slower paced, but transistor density isn't growing much and the core of the Law that is cost/transistor has increased with the last 2 or 3 iterations, instead of going down.

I've been following fab news for close to 2 decades already. I am familiar with all the major players in the market, but this article keeps mentioning SMIC.

Now I know SMIC since its creation, but afaik it has always been several nodes behind leading edge, and never scored any major contract. Without any large production contract, how does it get enough experience to even get to 7nm? UMC, their partner, pretty much gave up on 7nm already. TSMC has resisted all attempts at espionage. Is it from Samsung?

Well, there are lots of possible factors:

a) China is turning inward, maybe they're getting some state support, monetary, political, or otherwise; or at least benefiting from a lucky coincidence.

b) SMIC has been credibly accused of misappropriating TSMC secrets in the past, and settled.

c) I think a number of major Chinese manufacturing companies invest resources and money in them, possibly as some form of insurance policy.

d) The Chinese government does procure armaments, maybe SMIC does manufacturing they've been asked not to talk about.

> China is turning inward, maybe they're getting some state support, monetary, political, or otherwise;

This seems to be the most likely factor.

Yes, it is an explicit strategic policy of the Chinese government as part of "Made in China 2025" with state support (political and monetary).

https://en.wikipedia.org/wiki/Made_in_China_2025

A more direct motivation is recent U.S. sanctions on Chinese companies, the state support in semiconductor section has been boosted significantly, since decision-makers in China is now seeing the lack of state-of-art semiconductor manufacturing capabilities a critical threat to national security. Plausibly, developing the domestic semiconductor market to reduce foreign reliance is going to be a major goal.

As we see, SMIC has already withdrawn from New York Stock Exchange entirely [1], and purchased a 7nm EUV lithography machine from ASML for $120 million [2]!

[1] https://www.scmp.com/business/article/3011737/chinas-biggest...

[2] https://www.anandtech.com/show/13941/smics-14-nm-mass-produc...

I think the thing that makes it notable in this context is just a stated willingness to invest large sums of money down the road for new nodes, regardless of current position. I assume this is due to strategic subsidies by the government.

Moore's law is dead, but I don't think the story ends there. Now the incentives exist to explore alternatives to Silicon, which could yield many more years of big process improvements. While Silicon was scaling so rapidly there was little point in investing in alternatives. The free lunch is over, but the stage is set for the next act of the microprocessor revolution.

I wonder if architectural diversity will increase even further than it has.

It's already increased a bit in the microprocessor world with the rise of GPUs, but that "just" puts supercomputer-style vector processing in SBCs and laptops. It isn't as new of a concept as systolic arrays, for example; those can be fast even on slow hardware if you pick your problem right, just like how GPUs are only speed demons on certain tasks. Well, if we can't beat problems to death with increasing scalar speed, it might give us more incentives to design ever-more-specialized chips which solve specific problems extremely effectively even if they're comically useless for general-purpose computing.

Well, if we can't beat problems to death with increasing scalar speed

For those not immediately familiar with the terminology: "scalar" is Single Instructions, Single Data.

https://en.wikipedia.org/wiki/Flynn%27s_taxonomy

Ray Kurzweil has long predicted 3D computing chips would become a paradigm. I'm not talking about GPUs, but actually vertically stacked layers of transistors. https://www.kurzweilai.net/radical-new-vertically-integrated...

This has arguably already been appearing on the graphics side with stacked memory, but now Intel is getting serious about this approach: https://www.theverge.com/2019/1/7/18173001/intel-lakefield-f...

A big problem is heat. But stacked designs produce less heat overall, just in a smaller area. That can actually make heat dissipation more centralized and more efficient (due to higher thermal gradient) so I think it's a solvable problem.

I think if you can properly do a fully 3D circuit, you will probably also free up a lot of space to interleave heat pipes within.

Make Peltier cooling wires at the same transistor size throughout the chip to cool the interior and dump all the heat on the outside. Peltier coolers are supposed to be inefficient, but when you need to cool the interior of a cube a few millimeters across you don't have many options.

I think the issue there will be heat dissipation in general. IIRC, this was the plan for some of Intel's upcoming chips and is limiting the throughput frequencies as a result. This could mean more horizontal scaling, but limiting the frequencies to laptop/server levels. Though a lot of current games are more parallel, there's still a lot of gameplay on games that are optimized for single core frequency.

I do agree, the longer term will lead to stacking, I'm just not sure how far off that is in realistic terms, and if the complexities may outweigh the benefits in a lot of use cases.

The node shrinks are definitely slowing and have for a several years.

Suppose I have a million dollars. Could I make a fab [1] that can manufacture a Intel 286 processor (with feature size roughly 1.5 micrometer) or equivalent? If not, what year of semiconductor manufacturing technology could I replicate?

Wikipedia provides this rough estimate of feature size - year table: 10 µm – 1971 6 µm – 1974 3 µm – 1977 1.5 µm – 1982 1 µm – 1985 800 nm – 1989 600 nm – 1994 350 nm – 1995

What about only a 100K USD?

[1] capital costs only. Not labor.

No.

You couldn't even buy the cleanroom building for $1m

You may not need a cleanroom at that feature size today

Also yield isn't a big concern in a hobby project.

University labs often have cleanrooms that definitely do cost roughly on the order of low millions. And they are built to the standards of 2010s fabrication requirements. Replicating 1980s cleanroom requirements today would be a lot cheaper.

Edit: Page 64 of the pdf https://dokumente.unibw.de/pub/bscw.cgi/d9262701/01_History.... suggests in 1980 the total investment cost of a fab was $100million. I would expect that same tech could be replicated a lot cheaper today. A 100x improvement doesn't seem outrageous.

I don't see anything on that slight that indicates whether the numbers are inflation-adjusted or not. $100million in 1980 dollars is ~$300million in 2019 dollars. That's going to eat into your savings quite a bit.

I'm no expert, but a 100x savings seems pretty outrageous to me and 300x even more so.

Sam Zeloof [1] is a high school student who produced an integrated circuit in his garage. He says that the gate size is 175μm, but he has produced test features as small as 2μm. Looking at the photos of his lab, he has probably invested tens of thousands of dollars in the project.

So, that's one data point.

1. http://sam.zeloof.xyz/first-ic/

Also, check LibreSilicon [1], a free and open source semiconductor manufacturing process, currently in development. The target is 1 μm, but the developers said 0.5 μm should be possible. Here's a comprehensive introductory talk [2]. And as usual, the project is on GitHub [3]. If things went well, they said they planned to manufacture an open source RISC-V microcontroller, pin-compatible with Atmel AVR ATTiny.

[1] https://libresilicon.com

[2] https://media.ccc.de/v/35c3-9410-libresilicon

[3] https://github.com/libresilicon/process

> There are fewer foundries to choose from at the most advanced nodes

To the effect, only two. It is surprising just how fast it has turned into a duopoly.

Samsung and TSMC are now the Airbus and Boeing of semiconductor industry

> The cost to design a 3nm device ranges from $500 million to $1.5 billion, according to IBS. Process development costs ranges from $4 billion to $5 billion, while a fab runs $15 billion to $20 billion, according to IBS.

At these scales, very few players can afford to play, even if a breakthrough could net you a very comfortable position for many years.

Out of curiosity, do you know what factors are mainly driving the costs so high?

Thinking about it naively, I can guess at a few possibilities:

- it's highly labor-intensive

- it requires highly specialized skills that command incredibly high prices on the labor market

- it requires lots of prototyping iterations that require expensive materials

- the prototypes are produced on machinery with high opportunity costs

- IP licensing costs

I'm wondering if one of these in particular is the dominant cause, or if it's all of them in conjunction, or if there are other major factors I'm not thinking of.

the cost of highly specialized machinery is certainly a big driver. Plus that machinery is basically thrown away every time you go to a thinner process.

Also, figuring out how to maximize yields to an acceptable level must be a lot of experimentation.

Definitely not thrown away. Plenty of stuff still gets made on older processes. Fabs keep old lines alive for a long time, especially since each one is such a huge investment.

Today's R7 process is 2025's RPi.

I used to work on R&D on development of those expensive FAB machines. There was lots of expensive materials to meet extreme requirements. The process chambers were hot with corrosive gases. For example you couldn't use cheap o-rings. Instead of $30 standard o-rings, we would need $3000 chemical resistant o-rings that don't disintegrate with time. You had to trace down minute sources of contamination. And there was lots of iterations of prototyping to get things just right.

Lithography is actually a huge challenge, and is becoming extremely complex

https://semiengineering.com/7nm-fab-challenges/

A process cost is basically the 2 years of Fab time. And a Fab is expensive due to the capital equipment (your opportunity cost). A 10B Fab Costa about 2B per year, thus process development is 4B.

I think those design costs are nonsensical. There are major projects done by groups of 100 or fewer engineers. A really unique design can cost that much, but a licensed design built.on standard cells is less. That is how rocketchip, RiscV, and others get by. As an approximation, every M$ is 2 engineer years. A 100M$ design is...200 engineer years. With an ARM license and other IP, that is likely manageable.

There is a large infrastructure of design tools that keep design costs constrained per design. Fab costs are not so easily limited....

I just quit a gig at a semiconductor supplier that makes EUV light. Keep in mind this is just one major component in the chain:

- EUV comes from a plasma of metal created in a vacuum chamber.

- the plasma is created by concentrating a beam of light on a tiny pellet of molten metal

- that beam of light is a 25kw laser, which is borderline weapons-grade. To the point that countries hesitate to even allow it to be imported.

- the laser must be pulsed precisely to vaporize the metal as its flying through the chamber

- residue from the metal vapor quickly builds up and deteriorates the process

getting this stuff to work requires armies of engineers and scientists. the machines themselves are the size of a tour bus.

Intel is still ahead of them, right? Last I’ve heard they are moving pretty aggressively on their “7nm”, which is supposed to be at least as good as TSMC’s “5nm”.

Compare min metal pitch for Intel’s “10nm” (36nm) and TSMC’s “7nm” (40nm) [1]

[1] https://en.wikichip.org/wiki/10_nm_lithography_process

What does it mean to be ahead in 7nm when you are years behind in getting your 10nm process into acceptable yielding mass production?

I don’t see why they can’t be both behind on “10nm” and ahead on “7nm”.

Yes, they are substantially different processes.

True, but they seem to have been ahead on 10nm until they weren't, which calls into question claims about 7nm.

Then there's the question of why they aren't skipping 10nm if 7nm is so ahead.

And theres the question of why they can't 'scale up' their 7nm to do 10nm.

Presumably 10nm is cheaper to produce, so they can use that to make lower-end processors.

There are two technologies used in etching, UV and EUV. UV was designed for nodes upto 40 nm (approx). EUV can be used with accuracy of 13nm. EUV has been under development for more than a decade in several firms, so companies used several trickes to make use of UV for lower sizes. 10nm is the extreme end of it (I guess). For EUV this is standard range. It should work without any issues until 5nm and then special tricks would be used to make the pitch smaller.

So manufacturing 10n, with UV is much harder than manufacturing 7nm with EUV (although it is more expensive).

Yup, back in 2003 I was doing experimental work on creating better EUV mirrors and the amount of reflection achieved was way too low to support any machine with a design similar to UV machines. You needed either a (much) higher intensity source or fewer mirrors.

I've been out of that loop for a while, so I don't know how the design of the EUV machines turned out.

AFAIK, some (less than?) 2% of energy put into the EUV source ends up at the wafer. The EUV-source has been the biggest struggle for ASML from what I gathered in media.

Apparently, tiny droplets of tin are created by spinning some disk(s) and then those droplets are zapped with with a laser before they emit EUV. Those machines are crazy complex.

UV is under 1%, and EUV is under .01%

But don't TSMC use UV right now for their process? If so, UV vs EUV can't be the only reason for the mess they've gotten themselves in.

They've yet to master their own 10nm process let alone 7nm. I don't doubt their processes outdo the competitors on actual die shrinkage but they've been having a hell of a time of it.

From what I understand they are not really comparable like that. It’s like clock speed, there are a lot of games that can be played, and X 10nm can be much better than Y 7nm.

The problem with 10nm is that they were too ambitious and tried to do it without EUV. 7nm is being developed by a different team and does use EUV so it shouldn't suffer from the same delays.

I don't think that Intel is ahead of them. TSMC already started risk production of 5nm chips and plans to start high-volume manufacturing in 2020[0]. According to Intel roadmap they plan to launch 7nm product in 2021 (GPU)[1].

[0] https://www.anandtech.com/show/14175/tsmcs-5nm-euv-process-t...

[1] https://www.anandtech.com/show/14312/intel-process-technolog...

Although "5nm" and "7nm" look like physical measurements, they aren't; all they are is marketing labels, and the only thing you can be somewhat confident of is that if a single company has one process they call "5nm" and one they call "7nm" then the "5nm" one probably has physically smaller features and greater density of components on chip.

And although "2020" and "2021" look like actual dates, they aren't; all they are is marketing labels, because saying you're going to do something in 2020 is cheap.

So what we know is that TSMC say they are going to begin volume manufacturing of "5nm" chips in "2020" (reality: at some unknown date they will be making large quantities of chips on a process to which they have found it convenient to attach the label "5nm"), and that Intel say they are going to launch "7nm" chips in "2021" (reality: at some unknown date they will be making unknown quantities of chips on a process to which they have found it convenient to attach the label "7nm").

Whether TSMC's "2020" is really earlier than Intel's "2021", and whether TSCM's "5nm" is really denser than Intel's "7nm", who knows?

(I'd guess TSMC are in fact ahead, but this isn't a field where you want to be trusting manufacturers' announcements much.)

For what it's worth, the presentation we got from our vendor was 2020 for first 5nm silicon from TSMC.

> Samsung and TSMC are now the Airbus and Boeing of semiconductor industry

Then what is Intel?

Lockheed Martin?

McDonnell Douglas or maybe Hughes Aerospace?

If I understand it correctly, 3 nm is less than ten atoms. Cannot this make the technology much less reliable due to quantum effects and interference?

It's about 30 atoms, depending on the material. Silicon's covalent radius is 111 pm, so it's 27 silicon atoms. But the 3nm process node doesn't mean that all the features are 3nm wide; a lot of things are twice that wide in many processes. Sounds like 3nm is pretty weird, though, so all bets are off.

IBM fabricated single-atom transistors that worked with adequate reliability back in the 1990s, IIRC. I don't know how bad the noise problem you allude to really is.

But the covalent radius is not the crucial property here, the silicone lattice spacing is, and that's 0.5nm so a 2nm wide element is 4 atoms across.

Correction: The lattice spacing gives the size of the fundamental building block of the lattice, which includes several atoms. The nearest neighbour distance in the lattice is 0.235 nm.

Wikipedia has a nice picture of the lattice structure:

https://en.wikipedia.org/wiki/Diamond_cubic#/media/File:Visu...

Part 3 of the picture is a 3x3x3 block of elementary cells, for silicon this would be 1.63nm along each edge, so for a 2nm element you get a few more atoms in each direction.

Thank you both for the correction!

Node names stopped meaning anything a long time ago, it's not really 3nm, that's just the marketing name. Think 11 inch "Footlong" but more extreme.

That being said, direct S/D tunneling is expected to become an issue at channel lengths of around 1nm, although anisotropic carrier mass can be used to delay this further.

AFAIK yes. You start to run into problems because the area you're trying to make a transistor in might not contain one of the dopant atoms which determine the semiconductor type. I believe hot carrier injection becomes more of a problem as well. At some point you probably run into quantum effects as electrons just start tunneling where they're not supposed to.

On top of all that, the design rules become crazy at small dimensions. You can't just make a sharp bend in a wire because the high frequency component of the bend causes ringing in the interference pattern of the EUV laser.

* - I'm just a software guy with a BSEE... I'm curious what a semiconductor designer has to say about all this.

You end up with fully depleted devices to avoid dopant effects. And tunneling loss is already an issue, and is mitigated with better work function metal design.

Sharp bends don't happen because they cause large fields which in turn cause dielectric breakdown. Most critical metal layers are oriented in a single direction. 2D printing with EUV isn't really an issue.

There are three components which make the area of a cell that are used to infer the scaling. The fin pitch, the metal pith, and the cell height (track count). An older technology (22nm) might have a 9track, 40nm by 60nm size. 14nm would be 9T2842, 10 would be 7.5T2638, 7 would be 6.5T2638 with SDB, and 5 might be 5.5T2230

Numbers very approximate, but the key is that design compaction (which requires major physical integration changes) coupled with reduced key pitch shrink.

The nice part is that you tend to get more design innovation, because you are no longer competing with shrink. And the relative cost of additional masks and layers is low.

3nm node means feature sizes in the range of 20-30nm. Names don't mean so much anymore

Can someone explain why the supply voltage for traditional finFETs can't be taken below 0.75V as is quoted in the article? Are they just talking from a mass production yield perspective?

https://en.wikipedia.org/wiki/Threshold_voltage

I guess I was unclear. I am trying to understand why the threshold voltage can't be reduced below what came across as a hard limit of 0.75V. My guess was that even a finFET can't give you the channel control required to prevent the transistor from approaching a lower threshold voltage. Which means it's half-on when it's supposed to be off, which means you've got a lot more leakage. But surely you can tweak it a bit more: make the fin taller, wrap it around the channel a little bit? And then maybe get a slightly lower threshold voltage? Maybe it's just not worth the hassle and having gate all around is a better return.

These things are generally already tweaked way into the region of diminishing returns. Easy gains are all taken.

https://electronics.stackexchange.com/questions/286824/silic...

Thanks! But I guess my point below still stands, it works just fine, it's just leaky.

> IC design costs also continue to rise. The cost to design a 28nm planar device ranges from $10 million to $35 million, according to Gartner. In comparison, the cost to design a 7nm system-on-a-chip (SoC) ranges from $120 million to $420 million, according to Gartner.

Is the comparison here a device with the same number of transistors, a device with the same area, or something else entirely?

Because if that's the per-area cost, then the design cost per transistor has barely budged.

Why are nodes a linear step of 2nm?

It seems to me that going from 7nm to 5nm (a factor 1.4) is a smaller step than going from 5nm to 3nm (a factor 1.6666). Not just a smaller step in engineering effort, but also in effect size.

It's not a linear scale, it's just that we're still rounding to integers, so we're going from 7 to 5 instead of 4.9 and then to 3 instead of 3.5. Since we've long since departed from having node names correspond to any physical dimension or even a meaningful composite of critical dimensions, the only thing wrong with sticking to simple integer naming is that we might run out of smaller integers before we run out of ways to improve silicon fabrication.

Ah, so its a factor of sqrt(2) on the length scale, corresponding to a factor 2 of area and (I guess) a factor of 2 improvement in transistors/cm^2. Makes sense, thanks!

How long until you can get flagship smartphone performance under a Watt ?

You can get flagship from maybe 4 years ago under a watt today.

In future you can get current flagship under a watt too. But then the new flagship with it’s 5W consumption will be so much better.

Only asking because under a Watt you get reliable small solar powered SoC

Small solar powered like with calculators and their roughly 1” sq. solar power strip?

That would be amazing but probably not feasible with the kind of display people have come to expect on their smartphone.

Maybe they can figure out how to embed a solar panel into the display. I guess it would absorb light though so it may be hard to balance with a light emitting display. I wonder if one can be very specific on directionality for both emission (outward direction only) and absorption (inward coming light only.) Logically I would think the emission layer goes on top of the absorption layer.

This seems on the face of it possible. I do not know enough about the specifics if it is reasonable to do.

I could see it though. Just leave your phone face up on your desk during the day to have it charge.

I was just wondering about that. But light emissions would probably cancel solar intake.

Not that small. But say smartphone case sized solar panel.

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