I'm a huge Verilog fan, but VHDL has a bunch of higher level features that Verilog doesn't have. E.g. records, limited range integers, enum types etc.

SystemVerilog added these kind of features much later.

That said: there are a bunch of constructs where Verilog really shines, especially when it comes to bit twiddling.

When you care about open source tool flows, it's no contest: Verilog is far ahead on that front. That's currently the deciding factor for me.