> REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations
> Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations
> When a Link is Degraded on a Port due to PCIe* Signaling Issues, Correctable Receiver Errors May be Reported on The Neighboring Port
The 1st is related to ISA complexity, the 2nd and 3rd aren't.
Based on a quick scan, I think 24 of the first 100 errata are ISA-complexity related. So "meaningfully easier" might be justified, but many problems come from peripherals or the MMU rather than the instruction decoder.
[0] https://www.intel.com/content/dam/www/public/us/en/documents...