The base RISC-V ISA is indeed very small. However, to compete with ARM/MIPS/x86 usefully as an application core, one must include many standard extensions. All of which add comparable complexity to the ARM/MIPS feature which they ape. It feels wrong to assert then without some serious qualification that RISC-V is simpler or easier to verify. A RISC-V core is no more or less complex to verify than a comparably featured ARM/MIPS core.
That said, and open ISA like RISC-V can really lead the way in terms of shared verification IP. That is the benefit to an open ISA, not it's simplicity, but the fact that it becomes worthwhile for people to share their verification infrastructure. Unfortunately, I haven't seen much of this yet. riscv-formal is amazing, and the riscv-compliance suites are getting better, but proper constrained random stimulus generation and coverage collecton? Not yet, at least, not out there in the open source world. I really wish that Western Digital had included their verification infrastructure when they open sourced Swerv [1].
Really enjoyed the article otherwise!
0 - A reasonable person might disagree this claim is being so explicitly made, but that's what I took from it.