Given that it takes many NAND gates to be logically equivalent to the rest of logic, wouldn’t creating OR and AND gates directly reduce the number of transistors and therefore help Moore’s Law as well?
OR and AND cannot be built directly in CMOS technology. The most efficient way to build them is by combining a NOR/NAND with an inverter.
Edit: To clarify, I believe there are cell libraries that do have OR and AND, but the transistor count is the same as NOR/NAND + inverter, so it's a bit questionable whether there's really an advantage to using them.
No. Gates require varying numbers of transistors to implement in CMOS.
This idea is almost exactly backwards - logic is reduced to nand because nand requires the fewest transistors, not because CMOS can't (or couldn't) make anything else.
I've also heard whispers that the Movidius Myriad II (company later acquired by Intel) actually used some sort of monte carlo optimization simulations to design pieces of the chip. Instead of optimizing some of the more specialized computer/stereo vision algorithms themselves, they threw the testbench at a really complicated constraint solver/optimizer and it spit out designs based on physical simulations where the individual units looked nothing like the logic gates used by a human designer and far more like an analog circuit using semiconductors.
I had read about simulated annealing being used to optimize FPGA logic unit layouts.
I assumed something similar was used to optimize gate layouts but never thought about actually optimizing the transistor layouts independent of NAND. That sounds like a great idea!