IC Redesign Can Fuel Moore's Law | Hacker News Reader

IC Redesign Can Fuel Moore's Law

eetimes.com

46 pointsmindcrime26 comments

"To reduce power dissipation and power density significantly without sacrificing computing performance, we need to invent a new transistor, a logic device that can be an alternative to CMOS. It should operate under very low supply voltage, much lower than 0.5V—closer to 250mV or even 100mV."

Did I miss the part with the ideas about how to do that?

There is a 2nd page to the article with a chart of different post-CMOS transistor technologies under development.

Whoops! Thanks!

Am I mistaken in thinking most of the alternatives are no better than CMOS? The chart has diagonal lines for a reason - energy times time seems like a good measure - and most of the alternative are up and/or to the right. Even CMOS-HP and CMOS-LV are near the same line but trade power for speed. The option the author seems to like is almost on that same line but in the slower/lower power area.

Steep slope (less than 60 mV/dec subthreshold swing) transistors- TFETs,NC-FETs, etc.

I’m curious, have we moved passed NAND gate only ICs?

Given that it takes many NAND gates to be logically equivalent to the rest of logic, wouldn’t creating OR and AND gates directly reduce the number of transistors and therefore help Moore’s Law as well?

That's a really good question and I hope someone comes by to answer it. My guess is that people go beyond this and already design entire adders and stuff at the transistor level if they think it affects their bottleneck.

I'm not a silicon engineer (I just pretend to be one to get my vendors to skip me right to their engineers for support) but afaik, Intel has been using weird phenomenon in semiconductors for useful work for a decade at a "lower level" than the logic gates. It's why they've managed to stay ahead of competition even on equivalent nodes and also why they've dug themselves into a corner (since they cant decouple their fab from IC design to spin off a TSMC competitor). Their cell library is likely the most specialized on the planet.

I've also heard whispers that the Movidius Myriad II (company later acquired by Intel) actually used some sort of monte carlo optimization simulations to design pieces of the chip. Instead of optimizing some of the more specialized computer/stereo vision algorithms themselves, they threw the testbench at a really complicated constraint solver/optimizer and it spit out designs based on physical simulations where the individual units looked nothing like the logic gates used by a human designer and far more like an analog circuit using semiconductors.

Oh that’s cool!

I had read about simulated annealing being used to optimize FPGA logic unit layouts.

I assumed something similar was used to optimize gate layouts but never thought about actually optimizing the transistor layouts independent of NAND. That sounds like a great idea!

NOR gates are actually commonly used, as are AOIs/OAIs in many technologies (and or inverters, 3-input circuits that are common in adders).

OR and AND cannot be built directly in CMOS technology. The most efficient way to build them is by combining a NOR/NAND with an inverter.

Edit: To clarify, I believe there are cell libraries that do have OR and AND, but the transistor count is the same as NOR/NAND + inverter, so it's a bit questionable whether there's really an advantage to using them.

> wouldn’t creating OR and AND gates directly reduce the number of transistors

No. Gates require varying numbers of transistors to implement in CMOS.

This idea is almost exactly backwards - logic is reduced to nand because nand requires the fewest transistors, not because CMOS can't (or couldn't) make anything else.

There is no need to have "NAND gate only" ICs in CMOS. You can easily implement any AND-OR-only network followed by an invert (NOT) gate for the output. As a further example, pass transistor logic is an alternative which can be implemented using CMOS transmission gates, it does not use a NOT stage however this means that it will not restore the signal voltage for the next stage, unlike the usual sort of CMOS logic.

we often use 'nand-gates' as a metric - in cmos they're about the smallest useful gate (other than an inverter) you can make - (4 transistors) - it doesn't mean we build everything from nand-gates - in fact a std cell library usually has 30-100 gates in it and synthesis tools pick the right gates for the job as we compile up our chips

The OP is advocating for MESO - magneto-electric spin–orbit logic.

From Wikipedia - Magneto-Electric Spin-Orbit (MESO) is a technology for constructing scalable integrated circuits, which utilize spin–orbit transduction of electrons. It is intended as a replacement for the CMOS technology. Compared to CMOS, MESO circuits require less energy for switching, lower operating voltage, and feature a higher integration density.

More here: https://www.techspot.com/news/77688-intel-envisions-meso-log...

Nature article here: https://www.nature.com/articles/s41586-018-0770-2

DOI: 10.1038/s41586-018-0770-2

The article states that MESO was developed by the author's research group at Intel. To be clear, there's nothing especially new about research into beyond-CMOS tech. But as we all know, it's rare for this sort of research to have real consequences on actual products.

Whats the hold up with Gallium-Arsenid (instead of silicon)? The PN junction threshold is 0.3V (instead of 0.7V for silicon). This would disipate less heat than silican based IC’s. Anyone know the technical reasons why GaLliumArsenid isn’t feasable yet?

Likely the typical material sciences reasons, having to do with heat, strength, expansion, etc.

From my experience, its really brittle.

We’ve been working with GaAs for a long time. You likely have a fair bit of it in your phone. A few things prevent its use for advanced CMOS - base material quality is inferior to Si, it’s not available in 12” substrates, and the cost is high.

You will likely see material integration of III-V material systems into Si, rather than using standalone GaAs for logic.

1. As we move to lower nodes, high carrier mobility materials such as GaAs actually perform worse than silicon due to increased source/drain direct tunneling. See: https://ieeexplore.ieee.org/document/7479214

2. Most III-V materials have excellent electron mobility, making for great n-type transistors, but tend to have poor hole mobility which means bad p-type transistors. Germanium has high hole mobility, and it is already used in very small quantities to boost performance (see "germanium stressors")

3. Most III-Vs have no native oxide, nowadays at 28nm onwards due to the use of high-k dielectrics. However: Until recently, the growth of oxides on III-V materials without defects such as fermi level pinning was a Hard Problem.

That’s a great reference!

I suspect there's some fruit on the tree of oscillator based computing. In other words... design memory and gates the way people have been approaching quantum computing, with no focus on quantum coherence.

"Negative capacitance" designs could help. https://www.nature.com/articles/s41565-017-0010-1

I think the missing part here is "which of these technologies, if any, offer 4-5 generations of improvement?" - no one's going to make the decision to move to a new untested process for just one generation

It's time for the age of graphene. SV -> GV.

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