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Comment by aw1621107 | Hacker News Reader

The explanation I've seen most frequently is that process sizes aren't really comparable between fabs any more. In this case, that would mean that Intel's 10nm process is equivalent to another fab's 7nm process.

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Comparing processes between fabs might not make sense, but the real question is — does it still make sense within a single fab? If so, then it's still very much the case that Intel, for whatever reason, has been stagnant while AMD has been moving forward at a fair pace, which still lends credibility to the narrative that AMD is closing the gap and Intel is losing some of its lead. Of course, as has been the case for decades, it still remains to be seen whether this will translate into AMD taking more of the market.

Is (Transistor Count / Die Size) something that produces a meaningful number?

Not really. E.g. the AMD ZEN+ moved to a 12nm process but kept both transistor count and die size constant. They instead used the headroom to space features out and improve cooling.

I think the HDL guys were running around with their hair on fire for Spectre bugs, hence why it was a straight transistor shrink with next to no logic changes. It's previously unheard of to not take advantage of a process shrink with logic changes; so much of your logic decisions are ultimately rooted in the process node.

You could still specify the maximum possible transistor density for the process. It doesn't mean a concrete design actually has to use it. Or make it an SRAM bit, because caches take up the bulk of the area anyway.

Pretty much equivalent to SRAM cell density, which you can measure under a microscope.

Speaking of SRAM, it's interesting how much effort is devoted to keeping the logic busy so they don't have to spend chip area on cache.

It's a useful number but its not the whole story. Fitting more transistors into a given area lets you put more chips on a wafer which is good economically. And it correlates with performance but, for example, Intel has traditionally accepted more restrictive design rules in exchange for more performant transistors and that has hurt their effective transistor density even if their individual transistors have been fast.

It gives you a bound on the areal density of the transistors, which correlates with their switching and power performance.

The problem is you need to be able to produce it in volume. The original projected 10nm is better than TSMC 7nm, that is assuming the 2019 10nm is still the same, which rumoured is not. Will be up against TSMC 7nm+, the next generation of 7nm.

Let's just assume they are both equal in absolute terms. By Late 2019, Intel would have barely launched 10nm and possibly shipping in 30 - 50M quantity ( And I think even that is an optimistic number ). TSMC wold have shipped more than 300M 7nm across their entire 7nm generation.

And TSMC has 5nm ready in 2020. I don't think Intel will have their EUV 7nm ready even in 2021.

Combined with the fact there is exactly only ONE, one EUV equipment maker on the market, ASML. And they have limited capacity in producing these ASML machine. As far as I am aware all of the 2018 and 2019 capacity are already locked to Samsung and TSMC.

Yeah, but that's not a good one, since they have been using the same process for 4 years if I'm not mistaken.

Whatever metrics are used, they are stuck on it for way longer than they should.

Yeah, I don't think anyone would argue that Intel has been having issues in recent years shrinking their process. The interesting question would be whether other fabs would end up facing similar issues with their next process node.

The rumor I heard was that Intel's shrink to 14nm was pushed really hard, and as a result a lot of key talent quit. While I'm not sure if it's true, it would explain a lot.

I'm not trying to be snarky; I actually don't understand. Isn't a nanometer the same between fabs?

A nanometer is the same everywhere, but what you’re measuring isn’t. When they say 7nm, are they talking about the smallest feature they can produce, the minimum wire size, the minimum transistor size, the average transistor size, or...?

For an analogy, a GHz is a GHz everywhere but that doesn’t mean a 3GHz CPU is always faster than a 2GHz CPU.

If AMD can suggest that they are on smaller process size because they are measuring a smaller feature, why wouldn't Intel just start measuring the same feature on their chips? I have trouble believing they would stick to some principle about what is the right feature to measure at the cost losing out on marketing themselves.

7nm does not refer to any feature size. Process node names have continued to follow the pattern of the next node being named as roughly the current node divided by sqrt(2), even though density increases are no longer coming from simple uniform horizontal shrinks.

They might, just like the MHz marketing wars. But for now consumers don't care about "7nm" as a marketing figure enough for them to care if it's actually 7nm or not.

Like others wrote, there's no longer a standard for what the measurement actually means. Most structures aren't actually 7nm in a 7nm process.

For example, a typical metal pitch on the low metal layers is 40nm, meaning you get one wire every 40nm, or 25 wires in parallel in a 1um channel.

What Intel is calling 10nm does indeed appear to be close to the others' 7nm. Then again, Intel is seriously behind on 10nm, so the bottom line remains the same: they seem to have essentially lost their process advantage.

Then why do they continue to use it at all? It's like measuring your electric car in the number of pistons it has. We all agree process node numbers are meaningless now so why do we keep using it?

How about a number that actually relates to the performance and can be measured?

My best guess is a combination of historical inertia and the fact that the names are actually meaningful, just not in the way that one might naively expect as an outsider.

When the foundry sends you a design kit which contains all their design rules and tooling around a process, then this process has some codename that appears everywhere (think filenames, names of library elements, and so on). This codename tends to be something like GF14 (for GlobalFoundries' 14nm) or N7 (for TSMC's 7nm) plus cryptic suffixes for different revisions of the foundry process.

So the 14/12/10/7nm terms are actually part of the design engineers' everyday work flow. They just also filtered through to marketing for whatever reason.

I could imagine that at some point in the future, foundries will switch to a year-based versioning similar to what happened with a lot of software. So you'll have a GF2027 process and so on. That's pure speculation on my part though, and inertia is definitely a thing.

Nanometers is a marketing term now, just like frequency used to be a marketing term when talking about CPUs.

In reality, size of various features in a CPU differ widely. Intel 10nm could have a transistor gate pitch of 50nm, while TSMC 7nm could have a pitch of 60nm. All the meaningful parts you care about, like size of the transistor components and interconnects, are _not_ small, and it every company designs their own tweaks on these building blocks for reliability/manufacturability/performance/power/etc.

Read this and follow links: https://en.wikichip.org/wiki/7_nm_lithography_process

Those differences seem enormous.

SRAM bitcell, High-Density (HD)

    A Intel 14nm: 0.064  µm²
    B Intel 10nm: 0.0312 µm² 
    C TSMC  7nm:  0.027  µm²

A is what most current intel chips use, B is in limited production. C is what AMD will be using in 2019

Is B even in production at all?

AFAIK there's a single 10nm Intel processor available – the Core i3-8121U. Performance is sub-14nm though.

It is. But what exactly you measure in nanometers is different, depending on how you define the "size of the structures"

A nanometer is indeed a nanometer. The question is what exactly is being measured, and that is what differs.

Who's explanation is this? Do you have a link?

Unfortunately, I don't know. As I said, it's just the explanation I've seen most frequently when browsing HN, and I'm not knowledgeable enough to know where to find reliable sources. Sorry.

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