Are any Intel engineers on this thread saying, whelp if they can do 6 we may as well give up? Or does the lack of any data help you sleep soundly and skeptically?
Do they in real code?
No.
The Mill team claims (with no running general purpose code OR data of any sort) that they can. YMMV, but I bet Intel sleeps safe. Which sucks because I actually want innovation in computer architecture, which is a notoriously uninnovative industry, and the Mill has some genuinely good ideas, but I don't think they'll work here.
4 µop/cycle after fusion.
https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-W...
It is very dependent on the workload.
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CISC is very efficient. They do the most ops per transistor.
"CISC is very efficient" is a meaningless statement. The specific instruction set and its implementation is or is not efficient.