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Comment by mycall | Hacker News Reader

They are claiming up to 6 ILP: http://millcomputing.com/topic/introduction-to-the-mill-cpu-...

If true, that'd be a very high number. Intel can get 2 on some benchmarks, but system-average IPC tends towards 1. (In terms of instructions standardized for cross-platform comparison. I take data on ARM servers and I'm jellous of 1.)

Are any Intel engineers on this thread saying, whelp if they can do 6 we may as well give up? Or does the lack of any data help you sleep soundly and skeptically?

Sure. In theory Skylake can deliver ~8uOPs per cycle in parallel.

Do they in real code?

No.

The Mill team claims (with no running general purpose code OR data of any sort) that they can. YMMV, but I bet Intel sleeps safe. Which sucks because I actually want innovation in computer architecture, which is a notoriously uninnovative industry, and the Mill has some genuinely good ideas, but I don't think they'll work here.

> In theory Skylake can deliver ~8uOPs per cycle in parallel.

4 µop/cycle after fusion.

http://www.agner.org/optimize/blog/read.php?i=650

ILP and IPC are not the same thing. ILP (instruction-level parallelism) is the number of instructions executed in a non-stalled clock cycle. IPC (instructions per clock) is the average number of instructions executed per clock, including clock cycles spent waiting for main memory and recovering from branch mis-prediction.

See slide 44:

https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-W...

It is very dependent on the workload.

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