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HDL newbie here -- how does this compare to Chisel (Scala -> Verilog)?

Here are some module design equivalents: http://www.ujamjar.com/hardcaml/chisel.html

As far as performance of what it synthesises down to, I have no idea as I have used neither.

Are you complete newbie to HDL?

Not total newbie, I've played with System Verilog and Chisel. Done some fiddling in simulators. But never synthesized to FPGA, though I have a board here I'll find the time to play with someday. I'm a software guy dabbling in hardware.

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