HardCaml: Register Transfer Level Hardware Design in OCaml | Hacker News Reader

HardCaml: Register Transfer Level Hardware Design in OCaml

ujamjar.github.io

84 pointsedwintorok8 comments

I've coincidentally just ordered an Altera SoCKit to play with this more over the summer. There's a nice tutorial on getting started with HardCaml and the SoCKit at https://ocaml.io/w/HardCaml

What's the motivation for this? I've seen a few HDLs recently similar to this[1][2].

I'd love to know why someone would develop one of these HDLs rather than work with one of the "mainstream" HDLs (i.e. system verilog, VHDL, System C)?

[1] - http://www.clash-lang.org

[2] - https://chisel.eecs.berkeley.edu/

If you have ever worked with a mainstream HDL you know how frustrating they can be.

care to give an example?

I've worked plenty with HDLs (mainly system verilog) from large ASIC projects to smaller FPGA prototyping projects. I could guess at a couple ways these new HDLs could possibly address some of the pain points, but it's not clear that's even their purpose.

Normally when you write hardware designs in an HDL, you have to work at a level of abstraction slightly lower than C. Since the algorithm you actually want to encode in hardware is probably not that low-level, this will be very painful. Proceeding to verify that the cross-compiled C-to-HDL hardware design actually does the right thing is then an even more long and painful process.

It would be very nice if we could write our algorithms meant to be turned into hardware in a language whose level of abstraction matched that of the algorithms themselves, and then compile them down with a solid guarantee that what we wrote, should it pass some high-level compiler checks, will actually work, at least insofar as software usually works after passing the compiler in a high-level language.

HDL newbie here -- how does this compare to Chisel (Scala -> Verilog)?

Here are some module design equivalents: http://www.ujamjar.com/hardcaml/chisel.html

As far as performance of what it synthesises down to, I have no idea as I have used neither.

Are you complete newbie to HDL?

Not total newbie, I've played with System Verilog and Chisel. Done some fiddling in simulators. But never synthesized to FPGA, though I have a board here I'll find the time to play with someday. I'm a software guy dabbling in hardware.

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