To follow-up on my own point, once an x86 instruction has been decoded into a micro-op, it gets stored in a micro-op cache, where the vast majority of the frontend spends it's time fetching from. Additionally, "in flight" is a function of frontend width, Reorder buffer size, additional Out of order structures sizes and throughput depends on those plus the retire width. Additionally, IPC alone is a poor metric for performance analysis because run time is a factor of IPC and clock speed. M1 has higher IPC because it runs at around 3 GHz compared to x86 CPUs running at 4 or 5 GHz. Apple optimizes for IPC, they are all different tradeoffs. Lastly, Apple's cores are probably the biggest in the industry. Compare their new generation of cores, they had to jumbo-size every structure (much larger than most x86 cores). So while it is impressive from a design point, from a micro-architecture point their cores have ballooned in size and are on 5 nm. Their architects are very good, but not godly like I see many tech sites ascribe them to be.
Experience: Designed SPARC, ARM, and x86 CPUs