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shuklaayush

26 karma · joined August 26, 2020

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shuklaayush··on Pushing the limits of RISC-V emulation
Author here, thanks for all the comments, didn't expect this to get picked up.

I've been working on speeding up RISC-V emulation for work and wrote this up as I went. Still learning this space, so I'd be keen to hear from people who've worked on emulators or binary translation, especially where you think this approach falls short

shuklaayush··on Pushing the limits of RISC-V emulation
Neat, I guess this gets you the same output as a per-instruction translator without having to run an assembler and linker over the whole program. I should try this and add it to the post for completeness
shuklaayush··on Pushing the limits of RISC-V emulation
Yeah, I went back and forth on the title. It's definitely not an interpreter. I still think of emulation as the umbrella term though, running code for one architecture on another, with interpretation and dynamic/static recompilation being different ways to get there
shuklaayush··on Pushing the limits of RISC-V emulation
Hey, author here. That's fair, I didn't have the background. I knew interpreters would be slow, I just didn't expect it to still be ~10x after all the optimizations. After reading about it more though, that does seem to be the norm
shuklaayush··on Pushing the limits of RISC-V emulation
I’ve been working on speeding up RISC-V emulation for my work, and I wrote a detailed blog about my learning. For some benchmarks, it now reaches roughly 85% of equivalent native throughput on an Apple M3.

I’d appreciate feedback from people who have worked on emulators, binary translation, JIT/AOT compilers.