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I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.

rosscomputerguyon Aegis – open-source FPGA silicon

Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.

rosscomputerguyon Aegis – open-source FPGA silicon

You can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.

rosscomputerguyon Aegis – open-source FPGA silicon

Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.

I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.

rosscomputerguyon Aegis – open-source FPGA silicon

Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.