521 karma · joined June 21, 2016
Outside of Putin's delusions of grandeur for an empire that never existed I still fail to see ANY upside for Russia for this war.
Putin didn't have to invade! If he was truly worried about Russia's economy he could have (and should have) gone about instituting reforms/policies to encourage economic diversification and growth. I fail to see how even a successful invasion of Ukraine results in economic upside for Russia. They were doomed to fight an insurgency for years which costs money, or they're going to spend resources rebuilding a country they just fought a war in.
The US had that exact system up until about 1935 - when Social Security was founded. It turns out that if we let people save for their own retirement, the vast majority will choose not to.
But then again if roadies were really all that concerned about aero and efficiency they'd switch to recumbent bikes...
https://www.bloomberg.com/news/articles/2021-03-10/wall-stre...
https://www.uhnder.com/ - radar on a chip
Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques...
That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today.
- Octavo Systems puts Ti SOC's and PMIC's in a package with outside vendor DRAM and ROM chips. - NXP builds some auto parts with a mix of NXP chips on different process nodes and third party flash.
I spent a few years designing these types of systems. In my mind the the biggest value of a standard like this is to push companies to make it worth their while to sell "known-good-die" (KGD) or fully-tested die.
Modern chip manufacturing basically has a two part test flow - a partial test of each die on the wafer then after slicing and packaging each part goes through final test. Packaging is expensive and so imagine building a multi chip module which might have an SOC, DRAM, PMIC and FLASH bare dies and then it goes through final test and each of those dies had a 90% final test yield then the MCM might only have a 65% yield. That's a lot of money down the drain.....
If I built the same part using fully tested die then my yields should be closer to 95-99% - basically the failures are not due to bad silicon, but bad packaging....
Right now it's tough to get companies to spend the resources on a KGD test program because the market is just too small/scattered. A standard helps to build a market.
With that said - I haven't seen this standard yet. I just requested a copy. From the little info available on the website (https://www.uciexpress.org/) it sounds like it's just an IO interconnect standard - along the lines of something like MIPI DSI + D-PHY. That's a good start but the dream of "lego" like chips will require standardized foot prints and pinouts which may just never be feasible but there are people exploring this idea....