Universal Chiplet Interconnect Express UCIe 1.0 Launched
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Right now, most semiconductor companies who make an SoC for whatever purpose, will often license designs for common things like a DDR controller or a PCIe interface. But in literally every architecture meeting I've ever sat in ever, the senior manager bigwig always asks: "has this design been tested in silicon yet?" And for a very good reason! No one wants to make a chip only to find out that there's a show stopping errata on the new bleeding edge Ethernet controller design. So the architecture team inevitably settles on the current generation IO protocol, which turns into previous generation when the chip is product ready.
But if your IO controller controller is instead on a separate chiplet, that risk of show stopping errata becomes less impactful (at increased the cost of packaging.) The vendor can respin, or you can choose a different vendor all together. It also allows for greater flexibility in vendor selection and SKU offerings, as well as yield improvements. But I think those upsides are a bit more obvious.
Unfortunately, it could make the business of selling IPs like memory and IO controllers that much more cutthroat, since the cost of changing vendors dramatically decreases. But then again maybe not, since a respin would barely (directly) cost the customer any money.
It seems like interconnects are something you'd want to make as fast as possible in order to stay competitive. Standardizing on a technology not controlled by your company is likely to slow down your innovation. At best, this seems like a helping hand to smaller companies like Marvell which might not have the resources to design a competitive interconnect solution themselves.
Intel has already shipped a MCM with an Intel CPU and a AMD GPU, back in 2018.
That probably just used PCIe, since cache coherence wasn't needed.
See slide 109: https://www.darpa.mil/attachments/ERI-DAProposersDay_Consoli...
Well that's a terrifying thought...
I guess it depends on what you mean by interconnect. If you’re talking about >100GbE then the Marvell has a large market share in interconnect market for high speed Ethernet.
Regarding pitch I’m not sure what your comment is based on but it’s doubtful you’re correct since pitch tends to be limited by the XTALK considerations not by fabrication. Since we are all using the same fabs we can all achieve the same minimum pitch supported by the ecosystem. Having said that even the pitch at these speeds is measured in microns and has been for a long time.
I think what you probably mean is that Marvell’s devices use a lot of DSP and FEC for use in Ethernet. This is because those interfaces are much higher speed and include impairment compensation for both electrical and optical channels. The DSP and FEC add latency which in compute applications would be problematic.
- Octavo Systems puts Ti SOC's and PMIC's in a package with outside vendor DRAM and ROM chips. - NXP builds some auto parts with a mix of NXP chips on different process nodes and third party flash.
I spent a few years designing these types of systems. In my mind the the biggest value of a standard like this is to push companies to make it worth their while to sell "known-good-die" (KGD) or fully-tested die.
Modern chip manufacturing basically has a two part test flow - a partial test of each die on the wafer then after slicing and packaging each part goes through final test. Packaging is expensive and so imagine building a multi chip module which might have an SOC, DRAM, PMIC and FLASH bare dies and then it goes through final test and each of those dies had a 90% final test yield then the MCM might only have a 65% yield. That's a lot of money down the drain.....
If I built the same part using fully tested die then my yields should be closer to 95-99% - basically the failures are not due to bad silicon, but bad packaging....
Right now it's tough to get companies to spend the resources on a KGD test program because the market is just too small/scattered. A standard helps to build a market.
With that said - I haven't seen this standard yet. I just requested a copy. From the little info available on the website (https://www.uciexpress.org/) it sounds like it's just an IO interconnect standard - along the lines of something like MIPI DSI + D-PHY. That's a good start but the dream of "lego" like chips will require standardized foot prints and pinouts which may just never be feasible but there are people exploring this idea....
If it's physical chiplets, are there any integration problems that come from trying to combine chiplets from different fabs in a single package? Variations in chemistry? How do you safely and cleanly transport unencapsulated chiplets?
Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques...
That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today.
This part isn't new, or why this is significant. For example, AMD has been doing this since Zen 2 (Ryzen 2xxx), combining 14nm and 7nm components.
On the other hand, the top chip designers and foundries working together and standardizing is potentially very significant, though I reserve judgement until actual products are produced on this new standard.