244 karma · joined January 29, 2013
So absent a microcode update that outright fixes Meltdown, there will always be some level of slow-down for vulnerable devices. System calls now jump from user mode code to a stub kernel in "supervisor memory". The stub kernel then does a full context switch (touching %cr3 paging register and wiping a good portion of the TLB), and once the real kernel finishes, it does a full context switch back to the stub kernel. It's all terribly inefficient, and realistically it's unlikely that there will only be negligible performance impacts. It should also be noted that this "work-around" doesn't fix processor, it just makes it so that that there's nothing juicy in the supervisor memory.
You may have to learn to live with this for a while. Even if it takes Intel a month to design and validate a fix for Meltdown, prototype and mass production turn around times mean that no customer will have a processor that isn't vulnerable to Meltdown until April-June 2019.
Multimedia is the driving force behind increased data usage, and I think we'll continue to need more throughput until we no longer get any benefits from higher resolutions (aka when we have substantially more pixels than rods and cones in our eyes). At the moment a phone with a 4K display saturates your eyes at any distance greater than 2 feet from your face. I think a 16x PCIe 4.0 link will likely provide more than enough bandwidth to generate fully immersive VR experiences, so the question then becomes... why and when will we need optical PCIe 5.0 to quadruple the datarate of PCIe 4.0...
PCIe signals are generated by transceivers -- devices within chips that are specialized in signal conditioning e.g echo cancelling, emphasis/de-emphasis, dynamic impedance matching. These transceivers and the analog and digital techniques they implement get better with time. This is easily measurable by looking at the Bit Error Rate of data or by looking at eye diagrams (see slide 15). As data rates increase things like drive strengths, impedance mismatches, and a number of other properties of silicon will "close the eye" meaning the transmitted "0"s and "1"s are not different enough for them to be distinguished by a receiver enough of the time to successfully decode a packet. (PCIe is packet based, it's surprisingly somewhat similar to Ethernet). But essentially as our understanding and processes for manufacturing semiconductor devices increase, we're able to "open the eye" more, at which point the industry decides to increase data rates.
I'm planning on doing a mini series explaining the MATLAB, C, and VHDL design flow behind building a high performance hardware modem. The first article can be found here, https://www.nuand.com/blog/bladerf-vhdl-ads-b-decoder/ Questions or suggestions are welcome, I would like to use them to improve my writing style and this mini series!
[1] https://www-ssl.intel.com/content/www/us/en/processors/archi...
[1] https://en.wikipedia.org/wiki/Viterbi_algorithm [2] https://en.wikipedia.org/wiki/Low-density_parity-check_code
Having used all of those tools, I can say that KiCad and Eagle will remain relegated to the low layer count, and at most moderately populated PCBs. Altium still has issues with large designs, but it's got its advantages, it's very easy to work with industrial designers within the Altium ecosystem. Altium also supports some decent auto-routing and DFM tools but does not have a simulator of any kind.
Cadence's OrCAD and Allegro offerings, and Mentor Graphic's PADS suite have tools for everything from designing with microvia (laser etched single layer vias) to highly configurable constraint management tools that allow for configuring some very powerful auto-routers and interactive tools. The big two tools also have simulators like PSICE, and integration with RF design tools like Keysight ADS, Genesys, Momentum, Hyperlynx, and HFSS. If your design has any RF components or high speed buses like DDR, PCIe and USB, you need to run your designs through these tools to verify your design. Eagle, and KiCAD are great for breakout boards. Altium can be used for some pretty simple products. But I'd never use anything but Cadence or Mentor Graphics tools for anything that had a signal that operated at more than 50MHz.
In my three year history of taking credit card payments online there has never been a time when I was not made to bare the entire cost of the chargeback plus Stripe's chargeback fees. So I am wondering When, if ever, does the bank or the processor bare the costs of a fraudulent purchase?