lprib

It's probably hand written but they didn't reverse engineer the purpose of each wire, only the netlist. Some of them are labeled, eg `irdbus_normal`.

Sure it would probably be cheaper to chuck a cortex-A* or similar mid-range MCU in there. One advantage of FPGAs that it can achieve "perfect" emulation of a Z80 (or other) since it's running on the logic gate level. No software task latency, no extra sound buffering, etc. It can re-create the original clock-per-clock.

Using `unreachable()` instead of `assert()` for your preconditions without profiling first is just pre-loading the gun to shoot yourself in the foot in the future. When those preconditions are inevitably violated at some point, you will get random UB corruption rather than simply aborting as is the case for assert.

> What would be the alternative

That's the point, there is not alternative at the moment. Breaking up monopolies allows competition and an alternative provider when something like this happens.