kijiki

> So all traffic is routed over Shoreline and then enters downtown through Villa/Dana?

Yeah, they're planning to put a ramp from the Shoreline bridge over the tracks down to Evelyn to spread out the traffic, but right now people take Villa.

> Is there still pedestrian access from the northeast side of the Caltrain?

Yeah, all the crosswalks are still operational. The long term plan is to put a bike/ped tunnel under Central and to completely close off the Castro/Caltrain side.

> there've been times I've been stuck for 20 minutes trying to cross the 100 feet from Moffett to Castro in Mountain View, because the light timing never lined up with the train signals.

They've conveniently solved this by closing the Moffett->Castro side of that intersection entirely. You can still go Castro->Moffett, but they're planning on closing that to eliminate the grade crossing entirely.

qemu used to use that technique, but as you note, it was pretty brittle. They switched to the more traditional TCG backend.

Seconded enthusiastically. That dam tour is amazing. Did it in 2007 or so.

Expect potential weirdness though. My wife was wearing a (not particularly short) skirt, and the lady at the office selling tour tickets made her step back and spin around, then said she couldn't go in like that. There is a gift shop that sells dam branded pants, so she bought a pair and we were cleared to go in. After all that, one dude in the control room was watching soft-core porn on one of the control room computers.

The turbine shaft room is especially crazy, since they let you (at least back then) walk right up to a few inches away from the shaft mechanically transmitting 700 MW of power! You could reach out and touch it, but we didn't and I wouldn't recommend it.

Everyone?

Intel, at the time the unquestioned world leader in semiconductor fabrication was so unable to accurately predict the end of Dennard scaling that they rolled out the Pentium 4. "10Ghz by 2010!" was something they predicted publicly in earnest!

It, uhhh, didn't quite work out that way.

I arguably owe a successful career in tech to my dad seeing a $99 deal on a TI-99 after they were discontinued in the mid 80's and buying it just because he had had a shortwave receiver as a child and saw some weird similarity. Unbeknownst to him, it turned out my mother had been a FORTRAN programmer in the 70's (though she described it as working as a lab-tech in a bio lab), and taught me how to program it in its weird BASIC dialect.

I've never understood why Intel didn't just soft-disable AVX512 on P-cores until the OS writes a value to some MSR that means "I understand that only some cores have AVX512".

From the OS side, the change to support it is pretty simple. On the first #UD trap caused by an AVX512 instruction being missing, pin the process to just the P-cores and end the process's timeslice.

Lunar Lake Lenovo Carbon X1. If you get the IPS screen, you'll get even better than 12 hours.

I run kodi via OSMC on a Vera V.

It comes with a dedicated remote (though it does support CEC), which solves #1, at the cost of having an extra remote.

I mainly hit #2 when scrubbing, often (worse on some compression types than others), it'll just freeze frame for a minute before everything catches up. This may be because I'm serving the content via HTTP to the Vera V, I've been meaning to try NFS and/or SMB. Never had issues with playback itself, probably because the Vera V hardware and the OSMC/Kodi build are co-developed, so there is pretty much always hardware decode support.

#3 surprised me; Kodi supporting just using my directory layout is why I use it over something like Jellyfin! I just added the HTTP share, and then navigate Videos->files->my_http_share_name and I'm in my directory structure.

Most of the Intel cache partitioning things were driven primarily by Google. The holy grail was to colocate latency-sensitive tasks with bulk background tasks to increase cluster utilization.

It's not common, but it absolutely happens: https://www.courthousenews.com/man-behind-s-f-system-lockout...

Early in my career in the mid 2000s, the startup that was on the same floor as mine laid off a QA person, who then showed up the next day and fatally shot the CEO and head of HR. Our CEO called me and told me not to come in that day.

> How do these guys get the data in order and we dont?

LAGs stripe traffic across links at the packet level, whereas QSFP/OSFP lanes do so at the bit level.

Different sized packets on different LAG links will take different amounts of time to transmit. So when striping bits, you effectively have a single ordered queue, whereas when striping packets across links, there are multiple independent queues.

DACs are usually twin-ax, which is just 2 coax cables bundled. The shielding matters a lot, compared to unshielded twisted pairs.

Faster parallel DACs require more pairs of coax, and thus are thicker and more expensive.

It has a client/server mode. I used to run the server on my wrt54g and the GUI client on my desktop.

There was this: https://www.servethehome.com/insane-48-port-2-5gbe-2x-25gbe-...

But I have not been able to find a place to buy one.

A HRV or ERV, depending on how humid it is where you live will help immensely. Unfortunately hard to retrofit into existing construction.

This is really easy, just use Linux.

"German pharmaceutical firm Bayer was forced to give up its rights to the Aspirin trademark in the Treaty of Versailles, in 1919, which followed its defeat in World War One (it also lost the rights to Heroin, but in hindsight it's probably not so upset about that).

The punishment only applied to aspirin's use in victor nations the USA, UK and France, leaving Bayer's trademark still enforceable elsewhere."

https://www.bbc.com/news/business-27026704

> In other words, homeostatic feedback causes salt consumption to stay about the same by increased consumption of salty-tasting processed food.

I'd imagine that McDonalds/Wendys/etc don't view that as a bad thing...

> want to play around with scraping LLDP data but our switch software stack has a bug

It's written for Cumulus Linux, but it should be adaptable to other NOSes with some work: https://github.com/CumulusNetworks/ptm

You give it a graphviz dot file, and it uses LLDP to ensure that reality matches that file.

If the monitors are 3ft away from the musician, they're already looking at 3ms of latency just in the air between the monitor and their ear.

Thanks for the correction.

I hadn't thought of 1bpp because it isn't interesting on VGA hardware. But you're absolutely right about 4bpp having been a thing.

320x200 at 256 colors. X doesn't support any depth lower than 8bit, so VGA 640x480 wouldn't work.

> you sure this is the best solution?

No, but I've been using it without issues for close to 25 years.

I'm on Debian stable, not OpenBSD, but SpamAssassin + razor + pyzor works really well. Roughly 1 spam per month, and 1-2 false positives a year. This is for an email address that has been used and openly spread widely for 25+ years.

The real work is making sure that outbound mail gets delivered, but even that is just making sure you have a clean IP and setting up reverse DNS + DMARC/SPF/DKIM...

Apple's search is Google search. Google pays Apple $20 billion a year for that.

What?

MacOS in 2000 was still old MacOS, with no compositing at all. The NeXT derived version of MacOS was still in beta, and I tried it back then, it was very rough. Even once OSX shipped in 2001, it was still software composited. Quartz Extreme implemented GPU compositing in 10.2, which shipped in 2002.

Windows finally got a composited desktop in Vista, released in 2007. It was GPU accelerated from day one.

As long as you relink with relocations preserved in the final ELF binary, it should.

MIPS had a fully classic RISC MMU, TLB only. TLB miss resulted in a fault which the OS handled to walk whatever data structure they chose for memory mapping. They had the KSEG regions which let the (virtual mapped) kernel easily access physical mapped memory for the walk. Not sure if this changed with MIPS64, though KSEGs would have been much less costly in terms of address space there.

PPC (at least Book-E variants) had a more complicated setup where TLB misses did a hash table lookup in HW. If that missed as well, it faulted to the kernel to do the full walk. The trick PPC used was that the page fault handler ran with paging disabled entirely, so it could access physical memory directly while handling the miss, no KSEGs necessary.

No idea how SPARC handled this, but x86/x86-64/ARM all do this entirely in hardware, though in practice it is really microcode.

What charger and battery did you use?