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kassaneon MicroZig: Unified abstraction layer and HAL for Zig on several microcontrollers

So don't wait. Tarballs already available for testing[1] and an example using esp-idf.[2]

[1]: https://github.com/kassane/zig-espressif-bootstrap/releases

[2]: https://github.com/kassane/zig-esp-idf-sample

kassaneon MicroZig: Unified abstraction layer and HAL for Zig on several microcontrollers

Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for esp32 from the C2/C3/C6, H2 and the new P4 release.

I'm currently working on a fork of the zig toolchain with espressif-LLVM to support Xtensa.[1] It is now possible to test with esp-idf instead of microzig for baremetal (Blink) yet.

[1] https://gist.github.com/kassane/7bdb782a1984d0c6581ae7b44e1f...

kassaneon Zig-style generics are not well-suited for most languages

There are some projects trying to bring this experience. https://github.com/ibokuri/concepts https://github.com/mov-rax/zig-validate https://github.com/yrashk/zig-ctc