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jprx

649 karma · joined June 10, 2022

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jprx··on To study how chips work, MIT researchers built their own operating system
Haven't gotten around to it yet haha
jprx··on To study how chips work, MIT researchers built their own operating system
Hi everyone, Joseph (paper author) here. You can find Fractal on Github: https://github.com/jprx/fractal

The full paper, slides from my S&P talk, and all our experiment data can be found at the Fractal project website here: https://fractal-os.com

We've been building Fractal internally for a very long time (first commit was almost exactly 2 years ago), so it's exciting to finally share it with the world. Let me know what you think!

jprx··on MIT 6.5950 Secure Hardware Design – An open-source course on hardware attacks
You can find PDFs of the lectures as well as the reading list here:

https://shd.mit.edu/2025/calendar.html

https://shd.mit.edu/2025/lectureReadings.html

jprx··on MIT 6.5950 Secure Hardware Design – An open-source course on hardware attacks
Personally, I learned programming when I was a kid by watching YouTube tutorials + reading random Internet sources. When helping build SHD, it was important to me that we "paid it forward" & made all our lab materials open for everyone to learn from.

Hopefully someone out there finds it useful!

jprx··on MIT 6.5950 Secure Hardware Design – An open-source course on hardware attacks
We teach using Intel X86_64 CPUs for a variety of reasons

- Most academic research has been done on Intel systems, so it's easier for students reading papers to relate to their experiences in the labs

- X86_64 provides convenient cache flush and cycle measurement instructions in userspace

- Intel's strongly ordered memory model and cache inclusion policy makes cross-core side channels simpler to reason about

- Practically, it's easier to scale up server infrastructure on Intel (you can do most of the labs on inexpensive Intel-based Linux systems)

- For Rowhammer, our students attack one particular kind of DRAM that we have profiled and know works well with our machines

- Note that AMD's cache inclusion policy differs from Intel's- we only support Intel chips for now

Down the road I could see us moving to ARM for a few labs (perhaps a future PACMAN attack lab...?)

jprx··on MIT 6.5950 Secure Hardware Design – An open-source course on hardware attacks
Yes!

Our labs include building your own real spectre attack against the kernel, bypassing ASLR and building ROP chains with various side channels, finding and exploiting backdoors in a RISC-V CPU by building a hardware fuzzer, and more.

(source: I designed the Spectre lab plus a few others)

All our labs are fully open source for anyone to try: https://github.com/MATCHA-MIT/SHD-StarterCode

If you give them a try, please do let us know what you think! We genuinely want these activities to be fun and approachable (we designed them like a big CTF) and welcome feedback from the community.

jprx··on A buffer overflow in the XNU kernel
You get it!!
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Unwinding changes to the TLB on every mispredict would have a significant overhead and hurt overall performance. Removing valid data you just cached (speculatively or otherwise) is generally a bad idea.

User mode software requires a TLB (unless you want to do a page walk for every single instruction!)

Even if you could remove the TLB entirely from the CPU somehow, the attacker could just use the cache or some other microarchitectural structure.

jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Additionally, if can find a way to trick a user into installing a malicious kext, why even bother with PACMAN? You already have arbitrary kernel code execution!
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
You could maybe do it with lots of fences or just a ridiculous chain of NOPs after each branch such that the ROB is cleared before you have time to try to load a pointer speculatively.

In practice, both of these would probably kill performance, so I don't think either of these are great solutions. Recall we are targeting the kernel where everything needs to be as fast as possible.

jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Pretty much!

(There are a few aspects that make this challenging in practice, but that's the idea).

jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
ILL-INI!!!

1) Our attack does apply a brute force technique with the twist that crashes are suppressed via speculative execution. If you tried to brute force a PAC against the kernel, you'd instantly panic your device and have to reboot.

2) Given that we never sign anything (only try to verify a signed pointer), and that every authentication attempt happens under speculation, I'm not sure how you would rate limit this without absolutely destroying performance. Keep in mind the kernel is doing a whole lot more with PAC than just our attack (for example, every function's return address is also signed with PAC) so distinguishing valid uses from a PACMAN attack might be challenging.

I suppose you could track how many speculative PAC exceptions you got, but it's a little late to add that now isn't it? And it could also raise lots of false positives due to type confusion style mechanisms on valid mispredicted paths.

jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
This is a great question! What this means is that a software patch cannot fix the speculative execution behavior that causes the PACMAN issue since it is built directly into how the hardware operates.
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
You can think of it a lot like that! PAC is more advanced as you can describe what a pointer "should" do on access (aka is this a data or code pointer?).
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Hi! This is an interesting idea. However, there is a problem that arises- if you rotate the key, then old pointers now become invalid. And since the kernel is always alive and servicing requests (and contains structures with very long lifetimes) we don't believe this to be a practical solution.
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Hi! I think I can clear a few things up here.

Our goal is to demonstrate that we can learn the PAC for a kernel pointer from userspace. Just demonstrating that this is even possible is a big step in understanding of how mitigations like pointer authentication can be thought of in the spectre era.

We do not aim to be a zero day, but instead aim to be a way of thinking about attacks/ an attack methodology.

The timer used in the attack does not require a kext (we just use the kext for doing reverse engineering) but the attack itself never uses the kext timer. All of the attack logic lives in userspace.

Provided the attacker finds a suitable PACMAN Gadget in the kernel (and the requisite memory corruption bug), they can conduct our entire attack from userspace with our multithread timer. You are correct that the PACMAN Gadget we demonstrate in the paper does live in a kext we created, however, we believe PACMAN Gadgets are readily available for a determined attacker (our static analysis tool found 55,159 potential spots that could be turned into PACMAN Gadgets inside the 12.2.1 kernel).

Our paper is available at our website: https://pacmanattack.com/paper.pdf

jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
You hit the nail right on the head! That's exactly what we did :)
jprx··on MIT researchers uncover ‘unpatchable’ flaw in Apple M1 chips
Hi! Joseph (one of the authors) here. You can read more about our attack here: https://pacmanattack.com
jprx··on Apple M1 Affected by Pacman Hardware Vulnerability in Arm Pointer Authentication
Hi! Joseph (one of the authors) here.

The PDF is available here: https://pacmanattack.com/paper.pdf