Hacker News Reader

guepeon Japanese companies fight for share of EUV chip technology sector

Two crowns are owned by the US: design and verification/design software and hardware tooling (my career is in verification). That's why China is non-export list for all of chip-design tooling and why China is now investing into their own tooling. It will take them time (maybe 2 decades ?) to catch up on tooling.

guepeon Massachusetts voters pass right-to-repair expansion opening up car data

Tesla sells in Mass, despite the first "right to repair" bill. There is quite a bit of money in Boston area, I am pretty sure they will comply like they did for the first bill.

guepeon Zoom Rolling Out End-to-End Encryption Offering

IMHO, the acquisition was mainly for two reasons: - signaling, to its customers and the market that they are taking this issue seriously - management "cover-my-ass": if somehow the overhaul is taking longer than expected, someone can claim "we tried everything we could"

There are secondary benefits, the acquisition did bring some probably-helpful talent around encryption/infosec, but as you said the rollout seems really fast vs acquisition time for a product that size.

guepeon ‘Better Yield on 5nm Than 7nm’: TSMC Update on Defect Rates for N5

Yes I agree with your comments, I over simplified. However, regarding "most semi", it depends if we are talking about market value vs # chips. The CPU/GPU market is really much larger in $$$ than low-power embedded chips. Although it's changing again with AI inference...

guepeon ‘Better Yield on 5nm Than 7nm’: TSMC Update on Defect Rates for N5

Chips are not designed to have fault tolerance. The typical solution on large chips today is to have large number of identical units, and use fuses to deactivate some when they are faulty. This is called binning and how all manufacturers build their line of products. Design and validation of fault-tolerant chips is MUCH more involved, which slows down next-gen products a lot. It's in general better to simply use today's process ASAP, with no or little fault tolerance.

The exception is wafer-scale chips, which are chips that span multiple "reticles", i.e. the size of the masks used to manufacture normal chips.

I have a Ph.D. thesis linked to building a wafer scale chip (ala cerebras, although 10 years ago). And cerebras AFAIK is the FIRST commercial product using wafer-scale approaches. Maybe we will see more products ? I have doubts...

Note also that defect density varies depending on location of the chip on the wafer. There are areas with more defects on average, so it's not as simple as 1 number.

guepeon With oil cheap, Arab states cannot balance their books

Prices have dropped more frequently because of US shale oil. Electrification is a very small factor (yet).

guepeon Build your next app with a graph database

I agree. I could not get to the point where author states the advantages of graph database. If author is preaching, then it's not convincing to the audience at stake...

guepeon Ariane RISC-V CPU – An open source CPU capable of booting Linux

I know ZeBu very well and... "a bunch of FPGAs" is an understatement. It can go all the way to 1500 FPGAs !

guepeon Tin Plasma Extreme Ultraviolet Radiation Makes 5nm Integrated Circuits Possible

I had a similar idea of using synchrotron to generate very low wavelength light for lithography... I guess costs are an issue!

guepeon Astro's Elroy Personal EVTOL in Flight Testing

I don't think this could be a winning design: it's inefficient because it's really like a helicopter. IMHO, the ones with some sort of small wings and horizontal propellers have way more chance to succeed. Efficiency during horizontal travel is much better - and this is position where you spend most time - as well as increased max speed and lower noise during travel.

guepeon Ask HN: Who is hiring? (June 2018)