finfet1

We're not talking about achieving on-die chip speeds at the picosecond range here. We're talking about interface specifications between the CPU and the DRAM, USB, etc -- these things can be designed for based on specs, and you don't need a trise/tfall equal to 10% of your FO4 inverter delay to achieve this. These are board level specifications which can be achieved with medium tier off the shelf components. And if they can't be achieved at the latest DDRX specs, then just design for one generation behind to at least get something going in the community.

Perhaps a solution would be if the verilog cpu project provided a few specific model numbers for each part (obviously, choosing ones that are commonly available and lesser cost), so that public contributors can work towards a common implementation for said part.

Academia is probably keeping quiet since most of EE, CS, CE is heavily dependent on IEEE publications for reputation and career advancement and paper-reputation.

IEEE and IEEE Explore have been actively going after professors and forcing them to take down links to their own papers. In the past, many professors hosted pdf's on their websites for their papers -- this has only stopped because IEEE has been forcing them off. Just wanted to add this for those who think professors have 'suddenly become stingy' -- no, they aren't - they were forced to.

Totally agree. I have gone through academia and am now in industry; the other day I wanted to read and browse basic papers in IEEE Explore for basic knowledge on new topics. Since I am no longer a student, I am willing to pay money - as much as hundreds to get unlimited access. Instead, for hundreds, IEEE explore offers a measly ("generous") 25 downloads a month or some such non-sense It just seemed so miserly of them. We researchers had formerly given them pretty much free research to publish, and they turn their back on even legitimate paid avenues for us to get the papers. We are willing to pay; but where is the option?

Anyone that has gone through research and academia knows that you often need to browse many papers to even find the ones worth reading. 25 paper cap includes browsing PDFs; you will easily hit that cap in a single day simply through browsing.

IEEE and IEEE Explore can go something themselves. This is coming from a published IEEE author and academic researcher.

haha... self timed domino .. published like 10-15 years ago already.

this won't work for many reasons that everyone in the industry already knows. High fan-out back to many gates that are spatially distant means that you need not only complex routing, but also complex sizing of the feedback inverter. So.. this won't even fit in with automatic place and route of complex cells. And good luck doing this custom in an efficient way such as making it a semi standard cell library.

Furthermore, the feedback inverter only works in simple cases such as the cascaded gates you show, when the switching of the one gate depends only on one fan-out. If it depends on more than one fan-out, the feedback inverter essentially requires another logic gate in front of it, which simply just blew up your entire circuit size and any power savings you were attempting.