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dvas

147 karma · joined December 17, 2022

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dvas··on AI-assisted coding will change software engineering: hard truths
There are many ways of thinking and reasoning about the profession and what it means to each and every one of us.

Some of the buckets:

* The builders, don't care how they get the result.

* The crafters, those who care how they get to the results (vim vs emacs), and folks who enjoy looking at tiny tiny details deep in the stack.

* The get-it-done people, using standard IDE tools, stick with them, and it's a strict 9-5.

...

And many with types, and subtypes of each ^^.

In my opinion, many people have a passion for making computers to do cool things. Along the way, some of us have fallen into the mentality of using a particular tool or way of doing things and get stuck in our ways.

I think it's another tool that you must know how to utilize and utilize in a way that does not atrophy your skills in the long run. I personally use it for learning and allowing me to get an in on a knowledge topic which I can then pull on and verify that the information is correct.

dvas··on Logseq: A privacy-first, open-source knowledge base
Might not be for everyone, but using git to index markdown notes + linking it against cloud storage like dropbox/icloud to have it available on phones/tables have served me well over the last 5 years.
dvas··on Logseq: A privacy-first, open-source knowledge base
I think the best approach to take with personal knowledge bases or any knowledge data, is to have the ability to bring your data in and out as one pleases.

In my flow, I use a hybrid Zettelkasten-based approach to linking notes. vscode, zettlr, logseq, obsidian all render correctly. I am happy to see more tools which exhibit more of this "bring your own data" mantra.

dvas··on Online Cryptography Course (2017)
I would like to add the thought of looking at where these elliptic curves are deployed, things like embedded devices and implementations bitcoin-core libraries for say secp256k1 [0].

Ref:

[0] Optimized C library for EC operations on curve secp256k1

https://github.com/bitcoin-core/secp256k1

dvas··on Online Cryptography Course (2017)
Thanks for sharing Shane, and nice to see companies engaged with the community on a technical level!
dvas··on Ask HN: How to Make News Aggregation Work in 2024?
For personal use:

What works is a good plain old rss.

Delivered to my client of choice, via gui or cli. Skipping ads and clickbait articles to save me time.

With a wave of generated content flooding some automated systems, the best curation will be done by yourself by finding reliable sources to subscribe to.

dvas··on Mental health in software engineering
I think it is so important to be able to disconnect from whatever it is that we are doing, even for a very short period of time. Go for a walk, brew a coffee or simply close your eyes and breathe.

Many times, stress is created artificially. It hurts our performance and deteriorates our ability to think.

Encountered numerous situations where work was "urgent" and would likely land a contract or sales for the company, and everyone would be a superstar if they delivered this "crunch".

After 2 months of pulling all-nighters and sleeping for 3/4 hours, we deliver the project ahead of time. Apathy begins to set in after management/decision makers keep on giving these gifts we call "crunches".

To help the company and go the extra mile is something most of us have done in the past and will possibly do in the future. However, it's like the story of the boy who cried wolf, if everything is urgent and every task is to be done NOW, then there are bigger issues at play.

Like everything in life, there is usually a limit/budget of money, time and effort. By abusing these limits and tolerances, people will lose respect for the people crying wolf and will put less effort into their work.

dvas··on PCIe 7.0 Draft 0.5 Spec: 512 GB/s over PCIe x16 On Track For 2025
To go a bit deeper, while still keeping it at a very high level what changes were made between each generation:

PCIe 1.0 & PCIe 2.0:

Encoding: 8b/10b

PCIe 2.0 -> PCIe 3.0 transition:

Encoding changed from 8b/10b to 128b/130b, reducing bandwidth overhead from 20% to 1.54. Changes here in the actual PCB material to allow for higher frequencies. Like changing away from PCB material like FR-4 to something else [2].

PCIe 3.0, PCIe 4.0, PCIe 5.0:

Encoding: 128b/130b

There is plenty to dive deep on, things like:

- PCB Material for high-frequency signals (FR4 vs others?)

- Signal integrity

- Link Equalization

- Link Negotiation

Then decide which layer of PCIe to look at:

- Physical

- Data / Transmission

- Link Layer

- Transaction

A good place to read more is from the PCI-SIG FAQ section for each generation spec that explains how they managed to change the baud rate as you mentioned.

PCI-SIG, community responsible for developing and maintaining the standardized approach to peripheral component I/O data transfers.

PCIe 1.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 2.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 3.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 4.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 5.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 6.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

PCIe 7.0 : https://pcisig.com/faq?field_category_value%5B%5D=pci_expres...

[0] Optimizing PCIe High-Speed Signal Transmission — Dynamic Link Equalization https://www.graniteriverlabs.com/en-us/technical-blog/pcie-d...

[1] PCIe Link Training Overview, Texas Instruments

[2] PCIe Layout and Signal Routing https://electronics.stackexchange.com/questions/327902/pcie-...

dvas··on PCIe 7.0 Draft 0.5 Spec: 512 GB/s over PCIe x16 On Track For 2025
I think a quick 2-minute read on the changes around each generation gen1 -> gen4 example from 2016 will make it a bit clearer [0].

Things like packet encoding etc. Then a quick look at the signalling change of NRZ vs PAM4 in later generations.

Gen1 -> Gen5 used NRZ, PAM4 is used in PCIe6.0.

[0] Understanding Bandwidth: Back to Basics, Richard Solomon, 2016: https://www.synopsys.com/blogs/chip-design/pcie-gen1-speed-b...

dvas··on An Introduction to Knowledge Graphs
Not my area at all, just passing by and wondering to the extent and how they use knowledge graphs for drug discovery.

Some time back I had a peek at AstraZeneca's GitHub [0] and got me curious. I know in genomics they try to use custom hardware to accelerate the process using FPGAs and others [1].

Curious if anyone can shed light on knowledge graph use at scale is being accelerated.

[0] AstraZeneca; Awesome Drug Discovery Knowledge Graphs https://github.com/AstraZeneca/awesome-drug-discovery-knowle...

[1] Gene sequencing accelerates with custom hardware https://www.mewburn.com/news-insights/gene-sequencing-accele...

dvas··on gh-116167: Allow disabling the GIL
Extra links for the no gil work for anyone else curious about this [0], [1].

[0] Multithreaded Python without the GIL https://docs.google.com/document/d/18CXhDb1ygxg-YXNBJNzfzZsD...

[1] Github repo https://github.com/colesbury/nogil

dvas··on Ask HN: How to get into quantitative trading?
Lots of other great answers, another one I came across recently is FinGPT[0]. For backtesting there is zipline [1], but doesn't look like it's maintained anymore.

[0] FinGPT: Open-Source Financial Large Language Models https://github.com/AI4Finance-Foundation/FinGPT

[1] Zipline is a Pythonic algorithmic trading library https://github.com/quantopian/zipline

dvas··on Reverse-engineering the Yamaha DX7 synthesizer's sound chip from die photos (2021)
Awesome reply, and thank you for the well put together answer linking to resources and for sharing your experience.

For Cortex-A8 from [4] and the others you have linked, It makes sense to me now regarding the instruction passing data between registers, filling out the pipeline and then stalling.

Will have a peek at ARMv8/ARMv9 arch's and see what they did there regarding SVE/SVE2.

dvas··on Reverse-engineering the Yamaha DX7 synthesizer's sound chip from die photos (2021)
Got me curious regarding ARM latency, wonder if that was related to particular instructions which added more latency or transfers between the registers/memory subsystem internals. Also on the off-chance that you remember, did you inline intrinsics or let the compiler auto-optimize?

Interesting to test out on the ARM Mac, and see if different dependency chains show significant latency penalties / in with reorder buffer.

dvas··on Reverse-engineering the Yamaha DX7 synthesizer's sound chip from die photos (2021)
This is great! What a lovely read.

Reminds me back of my teenage years mesmerised by software/hardware synths, daws and everything and anything related to audio tech. Hours spent trying to understand different waves, oscillations, LFOs, modulation, AM, FM and so on and so forth. I could go on all day. Great memories.

Anyhow, would be interesting to go down a rabbit hole reading up on the waveform representation for the DX7. Now that I remember, I will go ahead and look for SH-101.

dvas··on Conditional Git Configuration
Useful when you want to have multiple git accounts changing based on the path. Thanks for the share! In my case it was changing the ssh key based on the project folder.
dvas··on Database Fundamentals
Enjoyed reading it! Great overview of different concepts involved while building DB's. From mentioning SIMD to squeeze out performance on a single machine all the way to consensus algorithms.

While on the topic of DB's, reliability and distributed systems. Formal methods and how they can be applied in these situations and formally apply to Database internals for anyone else wishing to read up on as another concept.

Interesting paper on the S3 team using TLA+ to model.

[0] Use of Formal Methods at Amazon Web Services https://lamport.azurewebsites.net/tla/formal-methods-amazon....

[1] How Amazon Web Services uses formal methods https://www.amazon.science/publications/how-amazon-web-servi...

dvas··on Reality has a surprising amount of detail (2017)
That's the thing with details; sometimes you don't know the extent or context in which they will occur.

Your perceptiveness at a particular moment could determine a good or not-so-good outcome. However, you may not have the expertise or familiarity in a domain to spot micro, mini, or normal details.

My personal takeaway is to be mindful when you are on autopilot to avoid missing details and to avoid keeping your blinders on.

dvas··on PCIe vs. CXL for Memory and Storage
I think the real world latency numbers will be interesting to see with PCIe 6.0/7.0 since adopting PAM4 modulation allows the greater bandwidth.

[0] Why Did PCIe 6.0 Adopt PAM4? There Are Many Reasons. https://blog.samtec.com/post/why-did-pcie-6-0-adopt-pam4-the...

dvas··on PCIe vs. CXL for Memory and Storage
CXL and its coherency mechanisms will be interesting to watch as the requirements for LLMs and related applications requiring large memory pools continue to grow. This includes some HPC related workloads also.

One of the use cases I have seen recently was driving down the total cost of DRAM in a larger-scale deployment of systems at AWS, Azure, Meta etc.

Pond [1] which is a memory pooling system, claims to achieve the desired performance and at the same time lowering costs as one example.

I think a look at the overall, bigger picture is important. For example considering how a system will be combined together with multiple GPU's, memory systems and other accelerators to meet the demands of applications, consider interconnects like NVLink [3] too.

For those interested, I have left a previous comment about experimenting with CXL on a local setup [0]

[0] https://news.ycombinator.com/item?id=37944691#37948761

[1] Pond: CXL-Based Memory Pooling Systems for Cloud Platforms https://arxiv.org/abs/2203.00241

[2] Intel Reveals the "What" and "Why" of CXL Interconnect, its Answer to NVLink https://www.techpowerup.com/254462/intel-reveals-the-what-an...

[3] NVLink and NVSwitch; The building blocks of advanced multi-GPU communication—within and between servers. https://www.nvidia.com/en-us/data-center/nvlink/

dvas··on Ask HN: Where do you sit?
Started on a standard generic office chair sitting for hours. Then decided that an ergonomic big-name brand chair would be my silver bullet.

The next step, sit/stand desk. But still had some aches as I would either stand for 3 hours or sit for 3 hours.

The current setup is a mix of sit/stand desk and regular short breaks every 30 minutes or so. Even a glance away for 1 or 2 minutes to stretch but still keep a mental image of the work intact so you don't lose focus and flow.

The key for me, reaching a point where stretching and movement are incorporated into my day.

dvas··on Libre Silicon – Free semiconductors for everyone
Indeed! I recently tried some basic examples from the likes of SiliconCompiler and related projects and found myself reading up and going down the rabbit hole of open-source hardware tooling [0]

[0] https://github.com/aolofsson/awesome-opensource-hardware

dvas··on Even a laptop can run RAM externally thanks to CXL
Under 3.1 Allocator Interface, there is a great point about reducing wear levelling by rebalancing the B+ tree operations to reduce the number of writes thus extending the lifespan of the hardware. Not much of a concern on the small scale, however in large deployments even single-digit improvements will make a difference.

Sometimes it becomes useful to appreciate the hardware and what it is doing, reminds me of the quote.

* You don't have to be an engineer to be a racing driver, but you do have to have Mechanical Sympathy *. Jackie Stewart

dvas··on Even a laptop can run RAM externally thanks to CXL
If anyone wishes to dive deeper and attempt some emulation* of CXL and to find out more, checkout both links as QEMU supports emulating CXL devices.

[0] Emulating CXL Shared Memory Devices in QEMU https://memverge.com/cxl-qemuemulating-cxl-shared-memory-dev...

[1] CXL support in QEMU https://www.qemu.org/docs/master/system/devices/cxl.html

dvas··on Even a laptop can run RAM externally thanks to CXL
Some support has been added to the Linux kernel like DAX [0] to avoid extra copy operations [0].

SNIA has some interesting talks regarding using non volatile memory and its applications (DBs). Where using pmem and DAX to directly to store logging operations [1].

[0] What is Direct-Access (DAX)? https://kb.pmem.io/faq/100000008-What-is-DAX/

[1] SDC2020: How can Persistent Memory Make Databases Faster, and How Could we go Ahead? https://www.youtube.com/watch?v=rTgITrVhpQM

dvas··on Awareness at Death
Always wondered if the likes of DMT or trace amounts of it contribute to these experiences similar to how adrenaline is produced during fight/flight response.

Could it be possible that the brain sensing no more blood is being supplied then triggers a mechanism to release this chemical (and in what quantities)? Wildly speculating as a layman, however, maybe there is a link between dream states / DMT production/synthesis and these experiences which are yet to be explored further.

dvas··on Ask HN: How to setup a distraction-free Linux setup for writing
Maybe this could be useful.

I had a similar need where I always wanted to be able to start writing at a moment's notice, ideally with a key-bind of some sort where I didn't have to wait for the editor splash screen and various indexing operations.

I have created a flow where a key-binded system command would invoke a script which did the following:

1. Create a new instance of a terminal in full-screen mode / maximised (key binding can allow you to open up a terminal instance with parameters to specify view options)

2. In the newly created instance, open up a command line editor (vim in my case).

^^ The above is a simple starting point, however, you could add extra steps like disabling the network interface for a set period in the script, adding templates to different key-binding invocations etc.

dvas··on A student asked how I keep us innovative – I don't
Socialize the design: "Find people who you think will be contrarian, and have them poke holes in the design"

Happy to see this mentioned! By involving everyone, the experienced engineers will usually ask the harder questions and test the assumption of your design and the juniors to learn and re-evaluate assumptions they have about building software. Almost a win-win for everyone.

Even though in these discussions there may be a social aspect where certain individuals are trying that much harder to find disadvantages of a proposed design (many reasons which readers are probably familiar with). However, I think this becomes a net positive to the overall engineering as everyone tries to bring their A-game to these discussions.

Anyhow, my experience has been that collectively reasoning about a design (assuming the team feels comfortable with criticism) will always get results quicker.

dvas··on Chuck Feeney has died
In my opinion, Feeney had a massive impact on Ireland with his contributions. A great example of what it means to give back.

Take an example such as a multiplier effect of 5 times, that $1 billion created at least $5 billion of value at a minimum and second-order effects economically that are harder to measure over time.

dvas··on Queueing Theory: An introduction for software development
Can almost use it as a checklist while balancing service level against the cost of resources needed to achieve the service.

A great tool in the toolbox to have while building software!

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