datameta

Cellophane is still used to refer to LDPE grocery bags in former soviet immigrant diaspora

Mostly vegetables, sizable amount of seafood, and rice (if we speak of coastal east asia generically)

Imagining an ancient theological order with ranks based on color coding...

I wonder what portion of power users will take the color dosplay to its fullest. I'd still settle for trying out one of the older B&W models.

Ah then I'm mistaken in my logic. However they're gaming the system while citing color e-ink R&D and/or patent procurement as the cost driver.

I'm surprised the accelerators of yore trick actually worked and balancing a trio is trivially more difficult than duo? I enjoy the idea of having tons of VRAM and system RAM and loading a big model and getting responses a few times per hour as long as its high quality

This might be a simple take but - smaller and more expensive?

GPT3 drove the AI Dungeon explosion iirc

What kind of interactions do you have? Brainstorming, knowledge framework, rubber duck debug plus? Help me understand please if you will because I have a 3090 sitting without a suitable rest of it all and I wonder invest or not?

Realistically, how useful is local LLM usage? What are your use cases, hardware, and models used?

And even if you pull out the issue with the whole root, you have to fill it with something worthwhile, nurturing, and sustainable to you. Otherwise the hole will get filled by the next best time-wasting activity.

USA REMOTE | NYC HYBRID

  Languages: C/C++, Python, JavaScript, Kotlin, VHDL, SystemVerilog
  Hardware: PowerPC, ESP32, STM32, iCE40, ECP5
  ML: TensorFlow Lite Micro, PyTorch, ONNX, OpenCV
  IoT: BLE, WiFi, MQTT, LoRa

  Resume: https://docs.google.com/document/d/18mjB1tIH5s-ZmiET_smUxbMo3FaiC637aW_us8P0U5I/edit?usp=drivesdk
  Email: dm@datameta.info

Hi, I'm an embedded systems engineer/architect bridging the full compute spectrum of ultra-low power IoT, edge systems, and HPC.

My latest projects have been in full-stack edge ML R&D, memory controller firmware dev for POWER servers, and chip bringup/testing for Z mainframes.

I'm passionate about modular synthesis and tinkering with all sorts of analog circuits and DSP. Currently upskilling in analog PCB design and refining my abilities in FPGA development. Also WIP on a 3D-printed robot arm to practice control systems and actuation.

Therac-25 is the poster child for this kind of failure mode. Formal verification and behavioral equivalences would be invaluable, I think, but I can't pretend I understand much about the underlying math of the former.

I'll be honest I couldn't bring myself to read the whole thing, but it leads me to hoping we never entrust vibe-coders to work on mission-critical systems...

Not a bad idea at face value but as opposed to seatbelts it introduces additional complexity that has to handle every eventuality including G forces from any direction, and still function perfectly. Probably has failure modes that increase injury risk. But this isn't a bad line of thought to go down, ultimately.

Fair point about the protection structures lagging non-linearly in equivalent process node. Though wouldn't CDM events still correlate with feature density since the charge distribution across the die (assuming it correlates with the total gate capacitance)? More gates (higher density) means more to discharge safely?

Actually, for latchup specifically - even with oversized protection, don't the triggering conditions get worse with scaling since the parasitic SCR structures in the core have tighter spacing?

The higher the feature density, the likelier a discharge of a given voltage will cause physical damage?

I define "in control" as dropping for the last 30 years

We don't need national guard in the capitol deployed. Completely fabricated claim that crime is out of control. Absolutely a move to gain power and create internal enemies to fight while a certain list of clients is being much discussed.

Right, instead of fomo over not using the extra features of utilizing the right flow - people tend to experience the want/need to incrementally increase complexity when using roll-your-own software

Humor aside, there are people in the US who do get arrested for misdemeanors on purpose just to spend the night in a warm jail, and those that try to get into prison to alleviate chronic homelessness

But housing a family of three...

Could it be nobody wanted to be first and overshadowed, nor the only one left out - and it cascaded after the first announcement? My first hunch, though, was that it had been agreed upon. Game theory I think tells us that releasing same day in the pattern ABC BCA CAB etc would be lowest risk and highest average gain?

I now eagerly await Sonnet 4.1, only because of this release.

I wouldn't like the takeaway from my comment to be that any extra intensity beyond daily walking is wasted. Instead my point is that for some, walking is one of the few exercises within reach that is sustainable with low injury risk.

I am also saying that for those new to the gym, starting with say 10-20 minutes every day is better in the long run than 1-1.5 hours three times a week before the body is acclimated or before proper form is developed. This lowers the risk of injury that could set back the health improvement endeavor.

p.s. dancing to underground industrial techno for a few hours is a great way to do calisthenics

The point is there are those for whom one of the only forms exercise within reach is walking but it isn't thought of as exercise. Not all people are able to do more intense cardio or lift weights. Regular walking can bootstrap the body toward other exercise.

Tai chi actually is another amazing tool - it is a dynamic calisthenics exercise that builds core strength, balance, and stretches connective tissue.

Walking is exercise. Never forget that.

Consistency over sporadic herculean efforts always wins out.

SEEKING WORK | USA REMOTE | NYC HYBRID

  Languages: C/C++, Python, JavaScript, Kotlin, VHDL, SystemVerilog
  Hardware: PowerPC, ESP32, STM32, iCE40, ECP5
  ML: TensorFlow Lite Micro, PyTorch, ONNX, OpenCV
  IoT: BLE, WiFi, MQTT, LoRa

  Resume: https://docs.google.com/document/d/18mjB1tIH5s-ZmiET_smUxbMo3FaiC637aW_us8P0U5I/edit?usp=drivesdk
  Email: dm@datameta.info

Hi, I'm an embedded systems engineer/architect bridging the full compute spectrum of ultra-low power IoT, edge systems, and HPC.

My latest projects have been in full-stack edge ML R&D, memory controller firmware dev for POWER servers, and chip bringup/testing for Z mainframes.

I'm passionate about modular synthesis and tinkering with all sorts of analog circuits and DSP. Currently upskilling in analog PCB design and refining my abilities in FPGA development. Also WIP on a 3D-printed robot arm to practice control systems and actuation.

USA REMOTE | NYC HYBRID

  Languages: C/C++, Python, JavaScript, Kotlin, VHDL, SystemVerilog
  Hardware: PowerPC, ESP32, STM32, iCE40, ECP5
  ML: TensorFlow Lite Micro, PyTorch, ONNX, OpenCV
  IoT: BLE, WiFi, MQTT, LoRa

  Resume: https://docs.google.com/document/d/18mjB1tIH5s-ZmiET_smUxbMo3FaiC637aW_us8P0U5I/edit?usp=drivesdk
  Email: dm@datameta.info

Hi, I'm an embedded systems engineer/architect bridging the full compute spectrum of ultra-low power IoT, edge systems, and HPC.

My latest projects have been in full-stack edge ML R&D, memory controller firmware dev for POWER servers, and chip bringup/testing for Z mainframes.

I'm passionate about modular synthesis and tinkering with all sorts of analog circuits and DSP. Currently upskilling in analog PCB design and refining my abilities in FPGA development. Also WIP on a 3D-printed robot arm to practice control systems and actuation.