Fair point about the protection structures lagging non-linearly in equivalent process node. Though wouldn't CDM events still correlate with feature density since the charge distribution across the die (assuming it correlates with the total gate capacitance)? More gates (higher density) means more to discharge safely?

Actually, for latchup specifically - even with oversized protection, don't the triggering conditions get worse with scaling since the parasitic SCR structures in the core have tighter spacing?

Both of these assertions are false, unless you can provide some appropriately limiting context. On-chip ESD countermeasures are microscopic, and often ablative — that is, they can become less effective with each exposure. Damage occurs most commonly at or near corners of conductors, and secondly between adjacent traces. The dielectric breakdown or material migration that occur, when not immediately catastrophic, may induce increased susceptibility, instability, or subtle changes in behaviour that are not easy to detect.