cokernel_hacker

Illinois owed UIUC somewhere around a half-billion dollars while I was a student (circa 2011). I remember my professors having to go on furlough because of this.

It's amazing how good of a school UIUC is in spite of the awful mismanagement of the state.

Out of curiosity, how familiar are you with CPS? I remember the dropout rate being ~ 50%. Apparently it is now closer to 70%.

I don't think Illinois stands up to the likes of London or New York.

Arguably the most versatile compiler in the world is EDG's.

One of its features is: "a C-generating back end, which can be used to generate C code for C++ programs"

source: https://www.edg.com/index.php?location=c_frontend

In fact, the Itanium C++ ABI (which has no relation to the architecture) specifically uses valid C identifiers to mangle C++ names to support products like EDG.

source: http://mentorembedded.github.io/cxx-abi/abi.html#mangling-ty...

Actually, Clang supports most MSVC extensions. Here are links to two of Clang's test for __uuidof: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCX... http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCX...

The seem to have a workable solution for Youtube: they support both HTML5 and flash.

This is definitely possible, I'll give an example using LLVM's IR

input:

  declare void @g()

  define void @f() {
    br i1 undef, label %if.end, label %if.else

  if.else:
    call void @g()
    br label %if.end

  if.end:
    ret void
  }

  

after optimizations:

  declare void @g()

  define void @f() {
  if.else:
    tail call void @g()
    ret void
  }

The state of the X86 memory model before 2009 was quite poor [1]. All Intel had to offer was a whitepaper on memory ordering and it contained terms which weren't defined like "causality" and "transitive visibility".

As a person who lives in these trenches, I cannot stop myself from pushing others to read the fantastic X86-TSO paper by Sewell et al [2]. It gives a clear, easily understood view of the memory model. Their earlier, more in-depth paper, is here [3].

[1] http://www.mpdiag.com/intel_arch.html [2] http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf [3] http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.pdf

What you are describing is a Branch Target Buffer (BTB).

While local and global predictors describe which direction a direct branch may take, they do little to help indirect branches.

Take the example jmp [rax]. While condition codes for direct branches can be speculated, the value contained within rax isn't easily speculated either.

However, we can make note of where jmp [rax] took us the last time we executed. This mapping from branch instruction address to target address is precisely what a BTB is.

As for when they were invented, I believe the first paper on them is Lee83; I'm pretty sure the original Pentium had one.

Lee83 http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/CSD-83-121.p...

LLVM received this award back in 2010: http://www.sigplan.org/Awards/Software/2010

Those of the OS X persuasion can find similar functionality in fs_usage.

https://developer.apple.com/library/mac/documentation/Darwin...

This version of Visual Studio still seems to have XP support.

It's not quite that bad. Instead, it's the number of bits used by the enumerators. This makes bitwise operations safe on enumerators because or'ing and the like will not result in using more bits than any enumerator.

Merging two compiler backends, despite both targeting the same architecture, is not a day in the park.

LLVM gives you several opportunities to make decisions on how lowering from LLVM IR to machine code will occur, it is not likely that both backends would have been able to handle the same sets of preconditions for each other.

A very obvious example to consider: relocations.

Relocations are tied very closely to the final object file format. I doubt Apple's ARM64 backend had any provisions to deal with the ELF relocations in the psABI and I similarly doubt that the AArch64 backend had any understanding on what kind of relocations were available to it if it were to target Mach-O.

It was almost certainly "Superoptimizer -- A Look at the Smallest Program" [1], authored by the ingenious Dr. Massalin.

Dr. Massalin is also responsible for "The Synthesis Kernel" [2], a kernel written around the idea of wringing out performance.

Definitely worth a look for speed demon-type programmers like compiler engineers.

[1] http://www.stanford.edu/class/cs343/resources/superoptimizer... [2] https://www.usenix.org/legacy/publications/compsystems/1988/...

There is already indication that this has occurred:

Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-...

Optimize signed icmp of -(zext V): http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-...

Optimize -x s< cst: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-...

What's neat is that not all of these end up needing the InstCombine pass to get optimized, some of them can be handled using InstSimplify. InstSimplify isn't a pass, it's an analysis that get's called upon many times in the middle of other passes, strengthening them.

Even if you could write perfect assembly, sticking it in your program makes it more difficult for optimizations to flow across the assembly you have written because it is opaque to the compiler.

Better yet, imagine that the compiler has performed value range propagation [1] to determine that the range checks, after inlining, were redundant or simply elidable. This would be infeasible if it were written in assembly.

[1] http://llvm.org/devmtg/2007-05/05-Lewycky-Predsimplify.pdf

Different kind of tagging.

salem is referring to how addresses are compared in the cache: http://en.wikipedia.org/wiki/CPU_cache#Virtual_tags_and_vhin...

you are referring to ASIDs which are the mechanism by which different address spaces can share space in the TLB at the same time: http://www.helenos.org/doc/design/html.chunked/mm.html#id253...

Microsoft's Singularity http://en.wikipedia.org/wiki/Singularity_(operating_system) project was able to eschew the MMU and use verification to prove that programs couldn't harm the kernel or each other.

Structuring a kernel like this makes the micro-kernel idea much more palatable as context switch overheads drop dramatically.

Looks like somebody added -Wswitch-bool just now: http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-2...

There is no evidence that Apple doesn't like these apps because they aren't able to recoup fees, there already exist iOS apps that let you move money from one person to another without Apple getting involved at all.

For example, I often use my bank's app to move money to and from my roommate. I should note that this involves no transaction cost at all.

From what little has been confirmed, the system we know about works "better" the more connections you feed into it.

I doubt they intended to find anyone directly using this information. Instead, what is more likely is that collecting data in these games might help identify "friends" of people considered suspicious via some other means.

Although now that I think of it, games like WoW and EVE Online do make for quite a milieu. I know that several of my colleagues play such games and with each other.

It certainly chills the spine a bit when you realize that there are people who've had this kind of data for quite some time, using it for who-knows-what...

So the agency played hardball but the guy didn't budge, then tried to rip him off? Their bad faith effort seems to deserve punitive damages, I hope he takes them to court.

Those results are from over a year ago [1].

[1] http://llvm.org/viewvc/llvm-project?view=revision&revision=1...

libcxx has not only implemented C++14 but they have also implemented all known defect reports at roughly the rate they get published!

http://libcxx.llvm.org/cxx1y_status.html

C++11 1.4 [intro.compliance]/p7 "A freestanding implementation is one in which execution may take place without the benefit of an operating system, and has an implementation-defined set of libraries that includes certain language-support libraries" [1]

C11 4 [conformance]/p6 "A conforming freestanding implementation shall accept any strictly conforming program in which the use of the features specified in the library clause (clause 7) is confined to the contents of the standard headers <float.h>, <iso646.h>, <limits.h>, <stdalign.h>, <stdarg.h>, <stdbool.h>, <stddef.h>, <stdint.h>, and <stdnoreturn.h>." [2]

[1] http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2011/n324... [2] http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1570.pdf

malloc is special in environments that aren't free-standing, the compiler can assume that the pointer that malloc returns doesn't alias any other at that point.

The original ZFS paper references WAFL wrt its similarity a number of times. It seems like the biggest distinction that the paper claimed was that ZFS had pooled storage and WAFL was network oriented.

WAFL's biggest idea of the day was "write-anywhere" (the WA in WAFL). Write-anywhere is another way of phrasing copy-on-write which is a fancy way of saying _never overwrite_.

The idea, while simple, can be built upon to yield features like cheap snapshots and reasonable data integrity.

Perhaps "clone" is a bit too much but the similarity is definitely there.

FWIW, the NetApp folks sued Oracle because they also thought it looked similar [2]

[1] http://users.soe.ucsc.edu/~scott/courses/Fall04/221/zfs_over...

[2] http://www.netapp.com/us/company/news/press-releases/news-re...

Off of the top of my head: CLOCK-Pro [1] - an approximation of LIRS [2]

It's quite popular, I remember that MySQL and one of the BSDs use it.

[1] http://www.cse.ohio-state.edu/hpcs/WWW/HTML/publications/pap...

[2] http://www.cse.ohio-state.edu/hpcs/WWW/HTML/publications/pap...

Neat. My reading of these changes imply that they finally made the L2ARC's info survive a reboot.

For some background:

ZFS, a modern WAFL clone [1], has a replacement algorithm called ARC [2] which can concisely be described as a hybridized MRU/MFU (Most Recently Used/Most Frequently Used) replacement algorithm to decide which pages make the most sense for keeping in memory. There is considerable literature surrounding replacement algorithm design, I have little to say about ARC other than it is patented [3] and can be outperformed by newer algorithms.

Note that this is quite different from the traditional approach of FS/buffer-cache design. One usually expects the OS kernel to manage the buffer-cache for you (OS X has it's Unified Buffer Cache (UBC), NT has it's Cache Manager (Cc), etc.). However ZFS includes it's own incredibly complex caching subsystem around. I do not know why they didn't want to improve or modify the Solaris kernel's segmap subsystem but there are consequences to this design. Notably, ZFS's memory usage is quite a bit higher because of ARC.

The idea of performing read-caching in memory with ARC seemed like such a good idea to the ZFS designers that they allow for a second level of ARC to take place: L2ARC. L2ARC essentially runs the ARC algorithm between SSDs and HDDs to, hopefully, speed up the performance of random reads in a ZFS storage pool.

Now to steer back towards what this code dump seems to be about. If you recall from before, ZFS's ARC is a replacement algorithm based on usage and it needs to know which things to put where. This so-called persistent L2ARC remembers where things were on a L2ARC device so that the storage pool can take advantage of the fact that data is on the SSD on, say, a reboot.

Huh? Why did this require extra code? Remember, ARC was about caching: it didn't need to remember anything. When coming back online, complicated things happen: transactions get replayed, metadata integrity needs to be rechecked, etc. Implementing a persistent cache that is crash safe is incredibly difficult but not uncommon: auto-tiering [4] solutions like Fusion Drive [5] have to provide this kind of safety.

[1] http://en.wikipedia.org/wiki/Write_Anywhere_File_Layout

[2] http://en.wikipedia.org/wiki/Adaptive_replacement_cache

[3] http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=6996...

[4] http://en.wikipedia.org/wiki/Automated_Tiered_Storage

[5] http://en.wikipedia.org/wiki/Fusion_Drive

cute.

  /% cat /proc/cpuinfo                                                            
  processor       : 0                                                             
  vendor_id       : GenuineIntel                                                  
  cpu family      : 5                                                             
  model           : 1                                                             
  model name      : Pentium 60/66                                                 
  stepping        : 3                                                             
  cpu MHz         : 1.301                                                         
  cache size      : 256 KB                                                        
  fdiv_bug        : no                                                            
  hlt_bug         : no                                                            
  f00f_bug        : no                                                            
  coma_bug        : no                                                            
  fpu             : yes                                                           
  fpu_exception   : yes                                                           
  cpuid level     : 2                                                             
  wp              : yes                                                           
  flags           : fpu pse tsc cx8 pge cmov                                      
  bogomips        : 2.60                                                          
  clflush size    : 32                                                            
  cache_alignment : 32                                                            
  address sizes   : 32 bits physical, 32 bits virtual                             
  power management:

Heh, 1.3 MHz on a Pentium 60.

I am afraid that you are "extremely wrong"

He was referring to Mac OS, not OS X, which did have an intel port http://en.wikipedia.org/wiki/Star_Trek_project