Intel memory ordering, fence instructions, and atomic operations (2009)

peeterjoot.wordpress.com

45 points·luu··7 comments

The state of the X86 memory model before 2009 was quite poor [1]. All Intel had to offer was a whitepaper on memory ordering and it contained terms which weren't defined like "causality" and "transitive visibility".

As a person who lives in these trenches, I cannot stop myself from pushing others to read the fantastic X86-TSO paper by Sewell et al [2]. It gives a clear, easily understood view of the memory model. Their earlier, more in-depth paper, is here [3].

[1] http://www.mpdiag.com/intel_arch.html [2] http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf [3] http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.pdf

Funny thing,

Just yesterday I did not know almost anything about memory models, cache coherence, etc. Then I've read this book/lecture [1], got interested and later found the same great articles by Peter Sewell[2], you've mentioned

And today I see it on hacker news :)

[1] http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2...

[2] http://www.cl.cam.ac.uk/~pes20/weakmemory/index.html

See also the Linux Kernel documentation on memory barriers in general: https://www.kernel.org/doc/Documentation/memory-barriers.txt

Does any of this apply on modern x86?

You mean compared with the 'ancient' x86 from 2009?

Yes. Intel has done a surprisingly large amount of optimization in their CPUs over the past few years.

Sure but there is no way that memory ordering would have been impacted by any of those.

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