WillFlux

I’ve written an introduction to FPGA development with a couple of Xilinx-based boards:

https://projectf.io/posts/hello-arty-1/

It’s hands-on rather that theoretical.

The Digital Antiquarian is also worth reading on the history of Lemmings:

https://www.filfre.net/2017/10/games-on-the-mersey-part-5-th...

We’ll see :D

Forthcoming posts will cover simple 3D modelling with texturing and lighting in hardware. But that’s still a long way from a GPU.

It’s something I’m looking into. The font seems to render thinner on some platforms, making it hard to read.

PLLs are common to many electronics system, if you’re looking for a primer, try https://www.analog.com/en/analog-dialogue/articles/phase-loc...

However, from the point of view of these designs, the PLL is an internal black box that allows us to generate an (almost) arbitrary clock frequency.

We choose a frequency to meet I/O or performance requirements. In this case a pixel clock of ~25 MHz: we have to meet this to generate a valid 640x480 video signal.

None of the Exploring FPGA Graphics designs uses a CPU: the logic is all in hardware, often a finite state machine. The trick is ensuring the hardware logic completes within one clock cycle. For 25MHz, each clock cycle is 40ns. If a design is too complex to meet timing, we can break it into multiple steps, similar to pipelining on a CPU[1].

You can also run different parts of a design at different clock frequencies, but this introduces the challenge of clock domain crossing[2].

For a low-end FPGA, like an Artix-7, you can expect to run a reasonably complex design at 100-200 MHz.

[1] https://en.wikipedia.org/wiki/Classic_RISC_pipeline

[2] https://en.wikipedia.org/wiki/Clock_domain_crossing

Alas, this is a surprisingly hard question to answer, at least for FPGA design.

Here are a few sites that helped me learn:

* https://www.fpga4fun.com

* http://fpgacpu.ca

* https://www.nandland.com/verilog/tutorials/index.html

* https://1bitsquared.com/pages/chat (Discord)

And a few interesting blogs:

* https://blackmesalabs.wordpress.com/

* https://tomverbeure.github.io

* http://labs.domipheus.com/blog/

None of the introductory FPGA books have impressed me, so I don’t have any recommendations there. Maybe some other HN readers will have some suggestions?

If you're referring to the original URL https://projectf.io/posts/fpga-graphics/, then there are no sprites involved. We define a square mathematically, then check whether it has collided with the edge of the screen. It's a quick way to produce animated graphics with minimal knowledge and code.

The second post on Pong https://projectf.io/posts/fpga-pong/ includes collision checking between the ball and paddles at the drawing level.

I plan to cover full sprite collisions and overlap in a future post. In the meantime, there is a post that covers sprites with transparency: https://projectf.io/posts/hardware-sprites/

I haven’t looked at the FPGA re-implementations, but I am familiar with Amiga hardware: http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_gui...

I’d strongly encourage you to finish your write up and post it. As you say, there is a dearth of decent FPGA material, especially for hobbyists and those trying to learn hardware design.

SystemVerilog has several useful additions for FPGA engineers, but tool support has been slow to materialise. For the moment, I’ve kept to the few features that Xilinx Vivado and Yosys http://www.clifford.at/yosys/ are both happy with, such as enums, logic data type, and always_ff etc.

I’ve not used VHDL in anger, so can’t give you a useful opinion there.

I assume you’re talking about FPGA Ad Astra? https://projectf.io/posts/fpga-ad-astra/

The first sprites post, https://projectf.io/posts/hardware-sprites/ does include 4-bit sprites, but again no overlapping.

I am planning another sprite post with overlapping coloured sprites combined with a framebuffer background. I will probably use approach 2, as you describe, but with hardware design, I’ve found that the best algorithm can surprise you in practice.

Original author here. I’ll do my best to answer any questions. Be gentle; this is my first time on the receiving end of Hacker News. :)

“The end of CentOS could have the unintended effect of undermining the demand for ultra-stable ‘enterprise’ distributions in general.”

That seems possible. Perhaps like the UNIX of old, Solaris et al, the ultra-stable ‘enterprise’ Linux distributions will retreat to large enterprise customers?

Both great demos. I recommend watching Eon from the Revision 2019 Amiga compo stream: https://www.youtube.com/watch?v=zwoyfH7TgEQ&feature=youtu.be...

Hearing the crowd react definitely adds to this one!

“This method has been used by the author (along with another program that optimizes code emulating state machines) to write the C library function printf in only 500 bytes.”

I wonder how big libc would have been if they applied Superoptimizer to all its functions.

Where did that number come from?

Looking at https://www.simulant.uk/shop/amiga-addict-magazine it says 341 more orders required, so 159 orders so far.

If you want to see what an Amiga 500 can do in the right hands:

https://www.youtube.com/watch?v=zwoyfH7TgEQ&t=3270s

Eon by TBL from Revision 2019.

“There is a theory which states that if ever anyone discovers exactly what the Universe is for and why it is here, it will instantly disappear and be replaced by something even more bizarre and inexplicable. There is another theory which states that this has already happened.”