Sheppy96

I wasn’t suggesting probing caches is the main cost, I only wanted to describe that there is a long journey to DRAM in current architectures of which signal propagation is such a small part.

You are totally right that if you can make the resultant communication speed faster you could theoretically do away with caches. However this approach wouldn’t solve that problem on its own. Also forget not that cache is expensive and DRAM is cheap!

Yes I’m aware that caches can be physically addressed and you could reorder the sequence I described. No you can’t skip the TLB, but a hit will be faster since you don’t have to perform translation.

Transmission time isn’t really the main issue, it’s more about the work required to get a memory request through the levels of the hierarchy to DRAM and back. Probing each level of cache, propagating through the miss queues, translation (maybe with TLB miss), waiting for the DRAM controller, etc.