Space radiation environments present severe problems in semiconductor devices for space use. Conventional space-use devices are fabricated with special radiation-hardened processes. However, it was not feasible to continue this method because it was difficult to maintain and manage the manufacturing processes. In addition, it will be necessary to utilize state-of-the-art commercial processes to improve the performance of integrated circuits for space use. HIREC established the Customer-Owned Tooling (COT) procedure for developing advanced LSI circuits for space use. Hardening techniques utilizing the hardness-by-design (HBD) approach are utilized to ameliorate Single-Event Effects SEE).* Moreover, a radiation-hardened ceramic package is utilized to reduce the influence of Total Ionization Dose (TID).