Nowadays, mostly architectural. Some design. Not as much process.

They call it "hardening-by-design" which translates to "not rad-hard, at all, just fault tolerant"

Architecturally, you put in a lot of fault tolerance. Multiple oscillators so you don't lose lock. More ECC for RAM. Modulo checks for arithmetic. The ability to reboot quickly and get back to operational from a checkpoint is useful. Voting on operations to detect failures.

Design-wise, you minimize nodes that can cause upsets. You put more charge on gates and only use static CMOS. Presumably, you use bipolar (which is current-driven rather than voltage driven like CMOS) anywhere you can without losing a lot of area (PLL's, I/O's, RF, analog circuitry).

Process-wise, insulating substrate is the obvious thing since it minimizes the collection of ionized charge. I doubt they do much more. Developing stable materials for semiconductor usage is really expensive, and not terribly profitable.

Here is a quote from the product spec about the radiation hardening technology that HIREC developed:

Space radiation environments present severe problems in semiconductor devices for space use. Conventional space-use devices are fabricated with special radiation-hardened processes. However, it was not feasible to continue this method because it was difficult to maintain and manage the manufacturing processes. In addition, it will be necessary to utilize state-of-the-art commercial processes to improve the performance of integrated circuits for space use. HIREC established the Customer-Owned Tooling (COT) procedure for developing advanced LSI circuits for space use. Hardening techniques utilizing the hardness-by-design (HBD) approach are utilized to ameliorate Single-Event Effects SEE).* Moreover, a radiation-hardened ceramic package is utilized to reduce the influence of Total Ionization Dose (TID).

From what I know the exact ways it's done are usually kept as trade secrets because it's a very difficult thing to do and you want to recoup all the research costs of it, but wikipedia has some high level ways it's done:

https://en.wikipedia.org/wiki/Radiation_hardening#Radiation-...

Primarily they use "silicon on insulator" fabrication, such as silicon on sapphire. Since the feature size on these chips is usually many revs behind the current state of the art that results in fairly large transistors on die which helps a bit as well. There are some other techniques used (such as designing to avoid latch-up) but the fabrication technology is the major difference.

As much as I hate slide decks as an information source, this one is actually moderately informative: http://meseec.ce.rit.edu/551-projects/fall2013/2-2.pdf