Additionally, the first blog post in this series can be found at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...
I've used this board for my own soft CPU (http://jamieiles.github.io/oldland-cpu/) and it's a rewarding project!
Please don't use initial blocks to initialize values, use an always block with reset. That will also solve the issue of having multiple drivers per signal (bad). Also, don't load memories from the RTL, do that from the test bench (using hierarchical references).
initial begin
$readmemh({`OLDLAND_ROM_PATH, "decode.hex"}, microcode, 0, 127);
rd_sel = 4'b0;
update_rd = 1'b0;
alu_opc = 5'b0;
branch_condition = 4'b0;
alu_op1_ra = 1'b0;
alu_op1_rb = 1'b0;
alu_op2_rb = 1'b0;
mem_load = 1'b0;
mem_store = 1'b0;
mem_width = 2'b0;
pc_plus_4_out = 32'b0;
instr_class = 2'b0;
is_call = 1'b0;
update_flags = 1'b0;
update_carry = 1'b0;
cr_sel = 3'b0;
write_cr = 1'b0;
spsr = 1'b0;
is_swi = 1'b0;
is_rfe = 1'b0;
i_valid = 1'b0;
cache_instr = 1'b0;
exception_start_out = 1'b0;If someone knows of a community like HN that can write great Verilog, let me know.
There are a lot more "news" esk hardware design places as well but I'm assuming you're looking closer to stack overflow/github of HDL rather than the slashdot/reddit of HDL?
If you want HDL best practices any of the resources you can get your hands on from http://www.sutherland-hdl.com/papers.html <-- those folks are excellent
and I would highly recommend this book: http://www.amazon.com/SystemVerilog-Verification-Learning-Te...
For the memory loading, I don't know how you'd infer a ROM another way - aren't hierarchical references only supported in simulation/test benches?
If your target wasn't an FPGA (but an ASIC), the initial block would be completely ignored, so who knows in what state your design would start. FPGAs are nice, they let you specify initial values. Real chips don't. Just put all initial values in your reset clause, in the same always block you assign those registers. Let the FPGA compiler optimize the logic if it can, or infer a mux if it must.
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=...
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,40...
The DE0-Nano-SoC, which has an FPGA and a dual-core Cortex A9 might be a good option if you wanted to get started with Altera parts:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=...
The analogous Xilinx board is probably the Zedboard:
Finally, you might consider the Lattice Semiconductor iCE40. There are two dev boards (small and large, both very cheap):
http://latticesemi.com/iCEstick
http://www.latticesemi.com/en/Products/DevelopmentBoardsAndK...
They are especially attractive since they have the only fully open source toolchain:
https://github.com/cseed/arachne-pnr
Have fun!